Dynamic Gate Research Articles

Dynamic Liquid Gating Artificially Spinning System for Self-Evolving Topographies and Microstructures.

Developments in spinning systems have triggered revolutions ranging from bioengineering tissue scaffolds to emerging smart wearable fabrics, but the structures of the spinning fibers are usually limited by intrinsic channel configurations and the "dead" nozzle's geometry. In contrast, natural living systems, such as a spider spinning apparatus, use a "live" gate to coordinate microstructures via shearing and expanding at both axial and radial directions. Herein, for the first time, we introduce a dynamic liquid gating effect in artificial systems to mimic the spinning in biological organisms. Theoretical modeling and experimental regime diagram demonstrate that the topographies and microstructures of the fibers self-evolve after passing through the liquid gate and they could be tuned over a wide range, which successfully exceeds the limits of current "dead" spinning channels. In particular, fibers with a periodic spindle-knot structure self-evolve from a water gate and show fast directional water collecting and intelligent sensing ability. The liquid gating design not only sheds new light on fiber structure control in multiple spatiotemporal dimensions but also contributes to the development of high-performance fibers with sophisticated functions.

Dynamically Modulating Gating Process of Nanoporous Membrane at Sub-2 Nm Scale

Gating properties of nanochannels, as a key nanofluidic behavior, holds huge applications in sensing, mass transportation and separation. It has been widely studied the terminal “open” and “close” states in response to changes of environments, for prepared nanochannels. Yet to date, it remains great challenge to control the dynamic gating process. Here in this manuscript, we modulate the dynamically electric gating process in polypyrrole (PPy)-based nanoporous membranes system at sub-2 nm speed. The nano-confinement environment renders the polymer chain with excellent electrochemical property and the polymer film swells or contracts in a controlled speed accompanied by a reversible counter-ion uptake or expulsion. With this switching process, the thickness of the polymer changes by 83%, resulting a fully closed gating state. Besides, we directly observe the successive polymer chain variation at nanoscale (ca. 10 nm) by the AFM topography in situ . This small operation voltages and ultra-high strain scope, along with biocompatible materials, make this design promising for smart nanorobot and wearable applications.

Thermally activated dynamic gating underlies higher gas adsorption at higher temperatures in metal–organic frameworks

Mechanism of higher gas adsorption at higher temperature is revealed using analysis of free energy barrier for gas diffusion across gated pore channels.

A method for transformation from dynamic fault tree to binary decision diagram

Dynamic fault tree (DFT) is a powerful modeling approach for reliability analysis of complex system with dynamic failure behaviors. In reality, the tree structure may be highly coupled either by shared basic events or by the high-level dynamic gates. Currently, the application of sequential binary decision diagram (SBDD)-based method for quantitative analysis of such highly coupled DFTs is mainly limited to DFTs whose dynamic gates locate in the bottom of the tree. Moreover, there is no efficient way dealing with the dependencies among different nodes of a SBDD 1-path. This paper makes an improvement to the SBDD-based approach. A generation procedure is proposed to directly construct the binary decision diagram (BDD) model for a DFT with arbitrary tree structure. During the construction, the sequential-dependent information of the tree is derived as several BDD nodes, each indicates a binary-sequential event representing the sequence of two occurred basic events. A topological sorting is applied on each 1-path of the resultant BDD to obtain its contained disjoint cut sequences. Based on this, both qualitative and quantitative analysis can be performed on the DFT with no limitations on tree structure, and its minimal cut sequence set (CSS) is obtained as disjoint. Examples are provided for verification and comparison, and the results illustrate the merits of the proposed approach.

Thermal Stress Reduction of Power MOSFET with Dynamic Gate Voltage Control and Circulation Current Injection in Electric Drive Application

While operating an electric drive under different load conditions, power switch devices experience thermal stress which provokes wear-out failures and compromises lifetime. In this paper, a model-based dynamic gate voltage control strategy is proposed to reduce the thermal stress by shaping the profile of conduction losses. Thermal stability criteria are investigated, which limit the gate voltage operating range; thus, current focalization and associated local heat up are avoided. After that, simulations and lifetime estimation are conducted for performance evaluation in two different operation scenarios, which show promising results at high speed operation conditions. Furthermore, a current injection method is applied for low-speed operating conditions to improve the compensation effort. This method is experimentally verified by using a custom proof-of-concept gate driver that supplies an adjustable three-level gate voltage. A three-phase electric drive is prototyped, on which power cycling tests are conducted. The junction temperature is measured and the results confirm the thermal control method.

Experimental Realization of Nonadiabatic Holonomic Single-Qubit Quantum Gates with Optimal Control in a Trapped Ion

Quantum computation with quantum gates induced by geometric phases is regarded as a promising strategy in fault tolerant quantum computation, due to its robustness against operational noises. However, because of the parametric restriction of previous schemes, the main robust advantage of holonomic quantum gates is smeared. Here, we experimentally demonstrate a solution scheme, demonstrating nonadiabatic holonomic single qubit quantum gates with optimal control in a trapped Yb ion based on three level systems with resonant drives, which also hold the advantages of fast evolution and convenient implementation. Compared with corresponding previous geometric gates and conventional dynamic gates, the superiority of our scheme is that it is more robust against control amplitude errors, which is confirmed by the measured gate infidelity through both quantum process tomography and random benchmarking methods. In addition, we also outline that nontrivial two qubit holonomic gates can also be realized within current experimental technologies. Therefore, our experiment validates the feasibility for this robust and fast holonomic quantum computation strategy.

Run‐time neuro‐fuzzy type‐2 controller for power optimisation of GP‐GPU architecture

The increasing demand for high-performance computing has emphasised the invocation of sophisticated multi/many-core computing architecture. Graphical Processing Unit (GPU) is considered to be an essential innovation in this regard as GPU offers a significant amount of parallelism in the execution of complex computing applications. The performance of GPUs in reducing the computational time of such applications is worth mentioning. Although GPUs appear to be a problem-solving solution for complex applications yet high power consumption has been a challenging problem, associated with this many-core computer architecture. Efficient resource management is a emerging and promising solution to this challenge; however, reducing the resources would degrade the system's overall performance. On the other hand, reducing the resources based on the analysis of workload can save significant power without degrading the system's overall performance. Therefore, a smart controller to optimise the resources of general purpose-GPU (GP-GPU) architecture is required. AFBRMC-2, a neuro-fuzzy type-2 based controller, is presented for GP-GPU architecture and, based on a feedback mechanism, keeps analysing the stats of processor and manages resources using dynamic voltage frequency scaling and core gating techniques. The proposed controller achieved up to 55% reduction in power consumption against various benchmarks on the NVIDIA TK1 GPU kit.

Quantifying bias and precision of kinetic parameter estimation on the PennPET Explorer, a long axial field-of-view scanner.

Long axial field-of-view (AFOV) PET scanners allow for full-body dynamic imaging in a single bed-position at very high sensitivity. However, the benefits for kinetic parameter estimation have yet to be studied. This work uses (1) a dynamic GATE simulation of [18F]-fluorothymidine (FLT) in a modified NEMA IQ phantom and (2) a lesion embedding study of spheres in a dynamic [18F]-fluorodeoxyglucose (FDG) human subject imaged on the PennPET Explorer. Both studies were designed using published kinetic data of lung and liver cancers and modeled using two tissue compartments. Data were reconstructed at various emulated doses. Sphere time-activity curves (TACs) were measured on resulting dynamic images, and TACs were fit using a two-tissue-compartment model (k4 ≠ 0) for the FLT study and both a two-tissue-compartment model (k4 = 0) and Patlak graphical analysis for the FDG study to estimate flux (Ki) and delivery (K1) parameters. Quantification of flux and K1 shows lower bias and better precision for both radiotracers on the long AFOV scanner, especially at low doses. Dynamic imaging on a long AFOV system can be achieved for a greater range of injected doses, as low as 0.5-2 mCi depending on the sphere size and flux, compared to a standard AFOV scanner, while maintaining good kinetic parameter estimation.

Digital Logic and Asynchronous Datapath With Heterogeneous TFET-MOSFET Structure for Ultralow-Energy Electronics

The tunnel field-effect transistor (TFET) is a promising solution for high energy-efficient circuits. Based on the band-to-band tunneling (BTBT) condition, fast switching characteristic with a steep subthreshold swing (SS) in the ultralow-voltage operation is feasible. Our prior work has demonstrated that the SS and ON-state current can be improved without leakage current penalty through the usage of SiGe low-bandgap material in the epitaxial tunnel layer (ETL). ETL-TFET is highly compatible with the CMOS process, enabling heterogeneous integration of TFET and MOSFET in the same technology. In this work, the circuit performance of ETL-TFET and fully depleted SOI (FDSOI) MOSFET is evaluated and compared in terms of energy and delay metrics. By combining the advantages of TFET and MOSFET, heterogeneous pMOS-NTFET dynamic logic gates are proposed. The pMOS-NTFET-based logic gates demonstrate the lowest energy consumption than other realizations. Asynchronous datapath is leveraged to combat the timing variations in the ultralow-voltage region. A 20.9%–33.9% energy reduction is achieved compared with the conventional MOSFET counterpart.

Universal nonadiabatic geometric gates protected by dynamical decoupling

Dynamical decoupling provides an effective method to protect nonadiabatic geometric quantum computation against environment-induced decoherence. Although some dynamical-decoupling-protected nonadiabatic geometric gates were proposed, they need to combine some other dynamical gates to perform universal quantum computation. In this paper we propose a scheme to realize a universal set of dynamical-decoupling-protected nonadiabatic geometric gates, which not only possesses the resilience to environment-induced decoherence but also allows us to perform universal quantum computation all by geometric operations.

Dynamic Gate Stress Induced Threshold Voltage Drift of Silicon Carbide MOSFET

For silicon carbide (SiC) power MOSFETs, threshold voltage drift is a remaining obstacle in their way to the market. This study experimentally investigates the drift under dynamic or switching gate stresses. It is shown that, beside static stress, the switching events can themselves be a driving force of the threshold voltage drift. However, this happens only when the dynamic gate stress is bipolar. The study extends to show that the dynamic stress induced drift can be sustained. The findings can be used in further work for managing and coping with the threshold voltage drift in device applications.

Dynamic Multi-view Combination for Image Classification

Multi-view learning is widely used in image classification tasks to better explore the discriminative information of different views. However, existing multi-view methods commonly rely on some pre-defined assumptions or fail to fully take advantage of the combination commonality between individual images. This paper presents an efficient dynamic multi-view combination approach to dynamically combine the discriminative power of different views. Specially, we firstly utilize a group of pre-trained CNNs to extract different views of an image. Secondly, we apply a dynamic gating module to the image, which will generate a weight vector of these views to model the image-level information for the multi-view learning. Finally, the weight vector and the views are combined for the classification. Experimental results and analysis on CIFAR-10 and ImageNet show the effectiveness of the proposed dynamic multi-view combination method (DMVC) for visual classification.

A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture

Polar codes are capacity-achieving channel codes and they have recently been adopted for fifth-generation (5G) enhanced mobile broadband (eMBB) control channels. Using successive cancellation list (SCL) decoding, the error-correction performance of polar codes can surpass state-of-the-art codes of a comparable length. However, the sequential SC decoding incurs a long latency, and list decoding requires complex tracking of candidates. We present a split-tree SCL decoder that works by dividing a polar code's decoding tree to sub-trees following a split-tree decoding algorithm. The sub-trees are decoded in parallel by smaller sub-decoders that reconcile their decisions in every decoding stage. The split-tree list decoder architecture improves the throughput and latency proportionally to the split factor. By exploiting under-utilized hardware resources, we apply frame interleaving to further increase throughput and employ dynamic clock gating to reduce energy. The results are demonstrated in a 0.64-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 40-nm test chip that implements a split-4, list-2, eight-frame-interleaved decoding architecture. The chip supports configurable code lengths up to 1024 bit and variable code rates. At 0.9 V and room temperature, the chip achieves 3.25 Gb/s with 42.8-mW power, or 13.2 pJ/b, and demonstrates competitive error-correction performance.

Active Gate Driver for Improving Current Sharing Performance of Paralleled High-Power SiC MOSFET Modules

Featuring higher switching speed and lower losses, the silicon carbide MOSFETs (SiC MOSFETs) are widely used in higher power density and higher efficiency power electronic applications as a new solution. Due to the limited current capability of a single module, more modules parallel-connected are necessary for higher power application. However, current sharing is the key obstacle. In this article, an active gate driver (AGD) for high-power SiC MOSFETs is presented to balance the currents of parallel-connected SiC MOSFET modules. The principle of the AGD is based on dynamic gate drive voltage adjustment to synchronize current edges and current slopes among parallel-connected SiC MOSFET modules automatically. Each AGD measures and controls the current of its SiC MOSFET module individually. No extra supervising control circuit is needed. In addition, the hardware and software configurations are independent of the system design and no restrictions on the number of SiC MOSFET modules connected in parallel exist. Finally, the switching performance of the AGD was experimentally verified on two parallel-connected SiC MOSFET modules in a multipulse test under constant and variable load currents. In addition, the effectiveness of AGD under different control topologies has been studied with simulation and verified using three parallel-connected SiC MOSFET modules.

Reliability Concern of 650-V Normally-OFF GaN Devices Under Reverse Freewheeling Stress

This brief first reports the behaviors of three different kinds of 650-V commercial normally- OFF GaN devices under repetitive reverse freewheeling stress, and the mechanisms are illustrated by experiments and mix-mode technology computer-aided design simulations. After the stress, unlike the stable behaviors of the device with ohmic-type metal/p-GaN gate stack and the device with cascode structure, there are degradations on the threshold voltage, the ON-state resistance, and the source-to-drain reverse voltage for the device with Schottky-type metal/p-GaN gate stack. During the freewheeling stress, there is a dynamic positive gate to drain voltage on the devices. Especially, the Schottky-type contact leads to a barrier height at metal/p-GaN junction and makes the p-GaN layer to become floating, which can lock the injected carriers. Worse more, there is a high electric field at the gate contact, which leads to the trapping of injected electrons. Once the stress is removed, more positive gate voltage is needed during the turn-on process to suppress the influences of unreleased electrons; as the results, the electrical parameters shift. Finally, the mix-mode simulation results prove the carrier injection, and the measured segmental shifts of gate leakage current prove the trapping process in p-GaN layer successfully.

Experimental Implementation of Universal Nonadiabatic Geometric Quantum Gates in a Superconducting Circuit.

Using geometric phases to realize noise-resilient quantum computing is an important method to enhance the control fidelity. In this work, we experimentally realize a universal nonadiabatic geometric quantum gate set in a superconducting qubit chain. We characterize the realized single- and two-qubit geometric gates with both quantum process tomography and randomized benchmarking methods. The measured average fidelities for the single-qubit rotation gates and two-qubit controlled-Z gate are 0.9977(1) and 0.977(9), respectively. Besides, we also experimentally demonstrate the noise-resilient feature of the realized single-qubit geometric gates by comparing their performance with the conventional dynamical gates with different types of errors in the control field. Thus, our experiment proves a way to achieve high-fidelity geometric quantum gates for robust quantum computation.

High-fidelity geometric gate for silicon-based spin qubits

High-fidelity manipulation is the key for the physical realization of fault-tolerant quantum computation. Here, we present a protocol to realize universal nonadiabatic geometric gates for silicon-based spin qubits. We find that the advantage of geometric gates over dynamical gates depends crucially on the evolution loop for the construction of the geometric phase. Under appropriate evolution loops, both the geometric single-qubit gates and the CNOT gate can outperform their dynamical counterparts for both systematic and detuning noises. We also perform randomized benchmarking using noise amplitudes consistent with experiments in silicon. For the static noise model, the averaged fidelities of geometric gates are around 99.90\% or above, while for the time-dependent $1/f$-type noise, the fidelities are around 99.98\% when only the detuning noise is present. We also show that the improvement in fidelities of the geometric gates over dynamical ones typically increases with the exponent $\alpha$ of the $1/f$ noise, and the ratio can be as high as 4 when $\alpha\approx 3$. Our results suggest that geometric gates with judiciously chosen evolution loops can be a powerful way to realize high-fidelity quantum gates.

Gating mechanism of elongating \u03b2-ketoacyl-ACP synthases

Carbon-carbon bond forming reactions are essential transformations in natural product biosynthesis. During de novo fatty acid and polyketide biosynthesis, β-ketoacyl-acyl carrier protein (ACP) synthases (KS), catalyze this process via a decarboxylative Claisen-like condensation reaction. KSs must recognize multiple chemically distinct ACPs and choreograph a ping-pong mechanism, often in an iterative fashion. Here, we report crystal structures of substrate mimetic bearing ACPs in complex with the elongating KSs from Escherichia coli, FabF and FabB, in order to better understand the stereochemical features governing substrate discrimination by KSs. Complemented by molecular dynamics (MD) simulations and mutagenesis studies, these structures reveal conformational states accessed during KS catalysis. These data taken together support a gating mechanism that regulates acyl-ACP binding and substrate delivery to the KS active site. Two active site loops undergo large conformational excursions during this dynamic gating mechanism and are likely evolutionarily conserved features in elongating KSs.

Towards Making the Most of BERT in Neural Machine Translation

GPT-2 and BERT demonstrate the effectiveness of using pre-trained language models (LMs) on various natural language processing tasks. However, LM fine-tuning often suffers from catastrophic forgetting when applied to resource-rich tasks. In this work, we introduce a concerted training framework (CTnmt) that is the key to integrate the pre-trained LMs to neural machine translation (NMT). Our proposed CTnmt} consists of three techniques: a) asymptotic distillation to ensure that the NMT model can retain the previous pre-trained knowledge; b) a dynamic switching gate to avoid catastrophic forgetting of pre-trained knowledge; and c) a strategy to adjust the learning paces according to a scheduled policy. Our experiments in machine translation show CTnmt gains of up to 3 BLEU score on the WMT14 English-German language pair which even surpasses the previous state-of-the-art pre-training aided NMT by 1.4 BLEU score. While for the large WMT14 English-French task with 40 millions of sentence-pairs, our base model still significantly improves upon the state-of-the-art Transformer big model by more than 1 BLEU score.

Asynchronous Dynamic Single-Flux Quantum Majority Gates

Among the major issues in modern large-scale rapid single-flux quantum (RSFQ) circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this article, asynchronous dynamic single-flux quantum majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents. Furthermore, asynchronous logic allows existing design algorithms to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in very large scale integration RSFQ circuits.