Dynamic Gate Research Articles

Modeling Static Delay Variations in Push–Pull CMOS Digital Logic Circuits Due to Electrical Disturbances in the Power Supply

Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic disturbance, such as might result from an electrical fast transient (EFT). Many soft errors come from changes in propagation delays through digital logic, which are caused by changes in the on-die power supply voltage. An analytical model was developed to predict timing variations in digital logic as a result of variations in the power supply voltage. The derivation of the analytical delay model is reported. The model was validated experimentally by applying EFTs to a ring oscillator built in a test IC. The predicted and measured ring oscillator frequencies (or periods) agreed within a relative error of less than 2.0%. To further validate the approach, the model was applied to test the response of more complex circuits consisting of NAND/NOR logic gates, binary adders, dynamic logic gates, and transmission gates. The circuits were fabricated on a 0.5 μm test IC and simulated on two additional process technologies (0.18 μm and 45 nm). The model performed well in each case with a maximum relative error of 5.6%, verifying the applicability of the model for analyzing complex logic circuits within a variety of process technologies. The proposed delay model can be used by IC design engineers to predict and understand the change in the propagation delay through logic circuits due to the disturbed power supply.

A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates

In this paper, a new charging scheme for reducing the power consumption of dynamic circuits is presented. The proposed technique is suitable for large fan-in gates where the dynamic node discharges frequently. Simulation results demonstrate that the proposed method is efficiently controlling the internal voltage swing and hence decreasing the power consumption of the wide fan-in OR gate without sacrificing other circuit parameters such as gate speed, area or noise immunity. The power-delay product of a simulated 8-input OR gate is reduced by 46%, compared to its conventional dynamic counterpart in the 90nm CMOS technology. Another important benefit of the proposed approach is 99X reduction in power dissipation of the gate load by limiting its switching activity. Furthermore, the delay of the proposed circuit experiences only 0.94% variation over 10% fluctuation in the threshold voltages of all transistors for a 32-bit OR gate. Using the proposed technique, a 40-bit tag comparator is simulated at 1GHz clock frequency. The power consumption of the designed circuit is as low as 1.987µW/MHz, while the delay and unity noise gain (UNG) of the circuit are 244ps and 499mV, respectively.

Dynamic Logic ALU Design with Reduced Switching Power

Background: The dynamic gates produce an extremely high power overhead due to their high switching activity if used in designing a compact and high speed circuit. This paper presents a dynamic logic basedarithmetic and logical unit that can realize reduced switching power to alleviate such a problem. Methods: This is achieved by employingthe modified dual VT domino logic and Limited Switch Dynamic Logic (LSDL) mechanisms. The LSDL technique provides a static like switching action which exhibits lesser area requirement and high speed performance. Findings: The design of the arithmetic and logical units using the conventional dynamic logic, modified dual VT domino logic and the limited switch dynamic logic are presented in the paper for validating the claim. Conclusion: Thesimulation results depict the fact that the use of the LSDL shows 52.86%reduction in the dynamic power in comparison with the conventional dynamic logic. The circuits are implemented using Cadence® Virtuoso tools and 45nm technology node library files. The power analyses are performed using Cadence® Virtuoso Spectre tool.

Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates

This paper presents accurate models for the analysis of fault trees based on stochastic logic. To produce the models, probabilistic analysis of static, dynamic and temporal gates is carried out and the probability models are converted to their equivalent stochastic logic gates. A hardware template is also designed for each stochastic logic gate. In the proposed method, users provide fault rates of basic events and immediately evaluate system reliability. Experimental results show that the proposed method is more accurate than previous methods using the proposed stochastic logic gates for dynamic and temporal fault trees. The formula was validated using the Markov model for exponential failure distribution events. The proposed model is applicable for both exponential and non-exponential distributions.

Reliability analysis of complex dynamic fault trees based on an adapted K.D. Heidtmann algorithm

Dynamic fault tree as a powerful analyzing tool is used to model systems having sequence- and function-dependent failure behaviors. The problem is how to quantify a complex dynamic fault tree where different dynamic gates coexist and are highly coupled. Existing analytical methods for analyzing dynamic fault trees are mainly Markov-based, inclusion–exclusion-based and sequential binary decision diagram–based approaches. Unfortunately, all these methods have their own shortcomings. As to the Markov-based method, it is frequently subjected to the problem of state-space explosion and only applicable for systems having components with exponential time-to-failure distributions. For the inclusion–exclusion-based method, it is often vulnerable to the problem of combinatorial explosion. As to the sequential binary decision diagram method, it cannot be directly applied to a complex dynamic fault tree where dynamic gates are highly coupled together, and its computational efficiency greatly depends on the chosen variable index. In this article, we put forward using an adapted K.D. Heidtmann algorithm to analyze the reliability of a complex dynamic fault tree. To improve the computational efficiency of our proposed method, products are ordered according to their lengths and compositions. To illustrate the applicability and advantages of the proposed method, a case study is analyzed. The results show the proposed method is reasonable and efficient.

Dynamic gate algorithm for multimode fiber Bragg grating sensor systems.

We propose a novel dynamic gate algorithm (DGA) for precise and accurate peak detection. The algorithm uses a threshold-determined detection window and center of gravity algorithm with bias compensation. We analyze the wavelength fit resolution of the DGA for different values of the signal-to-noise ratio and different peak shapes. Our simulations and experiments demonstrate that the DGA method is fast and robust with better stability and accuracy than conventional algorithms. This makes it very attractive for future implementation in sensing systems, especially based on multimode fiber Bragg gratings.

Dynamic fault tree analysis based on continuous-time Bayesian networks under fuzzy numbers

In the calculation of dynamic fault trees, the existing state space–based methods, such as Markov chain method, are basically global-state models, which make the solution procedure very complex. Bayesian networks have become a popular tool to build probability models and conduct inference for reliability design and analysis in various industry fields. The “state explosion” problem can be alleviated by Bayesian networks. Furthermore, to obtain sufficient failure data sets in real engineering systems is extremely difficult and thus causes the parametric uncertainty in failure data. To address these issues, a novel dynamic fault tree analysis method based on the continuous-time Bayesian networks under fuzzy numbers is proposed in this article. The probability distributions under fuzzy numbers for the output variable of dynamic logic gates are determined. The calculation of fuzzy failure probability of a system is presented. Finally, an example is given to demonstrate the effectiveness of the proposed method.

New method for multi-state system reliability analysis based on linear algebraic representation

Multi-state system is a certain complex system with failure criteria that are not limited to “normal or failure.” During the life cycle, both the system and each component inside have different states at any time point. State transition of the whole system depends on the structure function while that of any component has a certain mechanism. To directly express state transition processes of the whole system and all components, we develop a linear algebraic representation method. Based on this method, dynamic transition can be expressed by mathematic equations, in which information of both system structure function and components transition mechanism is embedded. Furthermore, the extended multi-state dynamic fault tree is introduced to multi-state system modeling. By means of the proposed linear algebraic representation, standard operating rules for both static and dynamic gates are generated by introducing two variables that are used to determine whether the transition occurs and which state the output would convert into, respectively. Then, a Monte Carlo simulation coupled with the multi-state dynamic fault tree method is proposed to calculate the reliability indices of a multi-state system. The proposed method is then validated with a dynamic fault tree problem from a literature. Finally, the servo turret system is taken as an example for the application of the proposed method.

Dynamic gate and substrate control charge pump circuits: a review

The article presents a study of different control technique based charge pump (CP) circuits for non-volatile memories. Dynamic gate control, substrate control and simultaneous dynamic gate with substrate control configurations are projected for enhancing the performance of conventional Dickson CP. Dynamic gate control reduces ON resistance of the charge transfer MOSFETs and charge is pumped with negligible loss. While substrate control removes substrate bias effect and improves voltage gain by controlling substrate voltage. Simultaneous gate and substrate control attains higher voltage gain by making CP circuit free of threshold voltage drop, substrate bias effect and providing lower ON resistance. However, the voltage gain is limited as clock level is constant for all the stages. To overcome this issue, a novel clock level shifting method is proposed and adapted in the dynamic gate and substrate control based CP. The voltage gain is improved as level shifters are used to increase the voltage level of clock pulses applied to the successive stages. Each control topology based four-stage CP circuits are designed and simulated in 0.18-μm standard CMOS technology. A detailed comparison of the CP circuit schemes is carried out in terms of parameters voltage gain, power efficiency, maximum output current, operating voltage range and operating frequency range. Simulation results show that the proposed CP provides maximum output voltage of 10.8 with 1.8 V supply voltage and lowest rise time of 14 µs.

Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design

Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.

A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating

Nonbinary LDPC (NB-LDPC) codes, defined over Galois field, offer better coding gain and a lower error floor than binary LDPC codes. However, the complex decoding and large memory requirement have prevented any practical chip implementations. We present a 1.22 Gb/s fully parallel decoder of a GF(64) (160, 80) regular-(2, 4) NB-LDPC code in 65 nm CMOS. The reduced number of edges in NB-LDPC code's factor graph permits a low wiring overhead in the fully parallel architecture. The throughput is further improved by a one-step look-ahead check node design that increases the clock frequency to 700 MHz, and the interleaving of variable node and check node operations that shortens one decoding iteration to 47 clock cycles. We allow each processing node to detect its own convergence and apply dynamic clock gating to save power. When all processing nodes have been clock gated, the decoder terminates and continues with the next input to increase the throughput to 1.22 Gb/s. The dynamic clock gating and decoder termination improve the energy efficiency to 3.03 nJ/b, or 259 pJ/b/iteration, at 1.0 V and 700 MHz. Voltage scaling to 675 mV improves the energy efficiency to 89 pJ/b/iteration for a throughput of 698 Mb/s at 400 MHz.

Effects of aging in Parkinson�s disease: Role of Ca channel in dopamine neuron computational model

Effects of aging in Parkinson�s disease: Role of Ca channel in dopamine neuron computational model

Establishing the Structural Rules for Ligand Recognition, Signaling and Assembly in Innate Immune Receptors

Type-I transmembrane Toll-like receptors (TLRs) are central to host defense against pathogens. Of the ten human TLRs, TLR4 is of particular interest given the complex mechanism required to recognize lipopolysaccharide (LPS) from the outer membranes of Gram-negative bacteria, culminating in transfer of LPS by membrane-bound CD14 to TLR4 in complex with the MD-2 coreceptor. Atomically detailed and enhanced sampling molecular simulations have recently enabled us to identify the allosteric switch in TLR4 activation; key to the switching mechanism is the remarkable conformational plasticity of the coreceptor, which we show is functionally conserved across an entire family of lipid recognition domains. As well as unravelling the experimentally-established structure-activity relationships of natural and synthetic LPS derivatives, we have combined simulations with biochemical data for TLR4 interaction with dietary fatty acids, challenging the long-accepted notion that the link between obesity, chronic inflammation, and insulin resistance occurs via this receptor. Related approaches have uncovered the mechanisms by which LPS derivatives are transferred from bacterial LPS aggregates to the CD14 coreceptor, and identified both the dynamic gating mechanism and final bound state of a hypothesized amino-terminal pocket, consistent with available NMR data. Finally, we have constructed multiscale models of truncated and full-length receptor libraries spanning the human TLR family, enabling observation of their transmembrane oligomerization. We correlate this with in vitro association and acceptor photobleaching FRET data for dimerization within live cells, helping to identify key stabilizing motifs and rationalize disruptive mutations. Our results reveal the structural basis for the tight coupling between extracellular, transmembrane, and intracellular domains required for higher order assembly, conformational change and adaptor recruitment. Collectively, these studies extend our mechanistic understanding of membrane receptor function, and pave the way for novel immunomodulatory therapeutic approaches.

Effects of aging in Parkinson�s disease: Role of L - type Ca channel in dopamine neuron computational model

Effects of aging in Parkinson�s disease: Role of L - type Ca channel in dopamine neuron computational model

Optoelectronic flexible logic gate based on a fiber laser

We implement a dynamic logic gate which consists of three elements: a chaotic fiber laser, a threshold controller and the output of the logic gate. The output signal of the fiber laser is sent to the logic gate input as to the threshold controller; threshold controller output signal is sent at the entrance of the logic gate and also feedback to the fiber laser which changes their dynamic behavior. The output of the logic gate consists of a difference amplifier; this compares the signals sent by the threshold controller and the fiber laser, resulting logic output that depend on an accessible parameter in threshold controller. We present the numerical results and experimental of the implementation of a dynamic logic gate using fiber laser, which demonstrates the ability to change the type of logic gate by modifying a parameter of threshold control.

Experimental realization of a dynamic squeezing gate

Squeezing is a nonlinear Gaussian operation that is the key component in construction of other nonlinear Gaussian gates. In our implementation of the squeezing gate, the amount and the orientation of the squeezing can be controlled by an external driving signal with 1 MHz operational bandwidth. This opens a brand new area of dynamic Gaussian processing. In particular, the gate can be immediately employed as the feed-forward needed for the deterministic implementation of the quantum cubic gate, which is a key piece of universal quantum information processing.

Quantification of Highly Coupled Dynamic Fault Tree Using IRVPM and SBDD

Dynamic fault tree (DFT) is a commonly used method to model systems having sequence-dependent and function-dependent failure behaviors. The failure structure function of a DFT can be expressed by logic OR of all minimal cut sequences, that is, minimal cut sequence set (MCSS). The occurrence probability to the top event of a DFT can be calculated using inclusion–exclusion (IE) principle based on enumerating the MCSS. However, the IE-based approach would have exponential evaluation complexity. Then, a sequential binary decision diagram (SBDD)-based method is proposed and successfully applied to analyze simple dynamic systems. This method is more efficient than IE-based method in asymptotic analysis. But this method cannot handle complex systems modeled by different highly coupled dynamic gates. In this paper, we put forward using Independent Random Variable Probabilistic Model-based plus SBDD-based methods to quantify an MCSS to obtain the failure probability of a complex DFT. The results obtained by the proposed method are exactly matched with those obtained by the existing methods. In addition, this method enhances the analyzing ability of the original SBDD and retains the advantage of high computational efficiency. The application and advantage of our proposed method is demonstrated by a case study. Copyright © 2014 John Wiley & Sons, Ltd.

Probabilistic model–based multi-integration formulas for quantifying a generalized minimal cut sequence

Many sequence- and function-dependent failure behaviors may exist in fault-tolerant systems, in which the failure of the systems depends not only on the combination of basic events but also on their failure sequences. Such systems can be modeled by dynamic fault tree with Priority AND gate, Spare gate, Sequence Enforcing gate and Functional Dependence gate. The existing analytical methods for analyzing these dynamic gates are mainly Markov-based or inclusion–exclusion-based approaches. Compared with Markov approaches, the inclusion–exclusion-based method presents notable advantages. However, to the author’s knowledge, no references by far have presented general multi-integration formulas applicable for solving a generalized minimal cut sequence, which is an unavoidable problem in inclusion–exclusion-based method. In this article, new multi-integration formulas are proposed based on traditional probabilistic models, which are applicable for solving a generalized minimal cut sequence as well as any dynamic gate. The rigorous derivation processes are given. The application and advantages of our proposed approach are demonstrated through a case study and the results indicate our proposed approach is reasonable.

Progress in SiC MOSFET Reliability

In this work, we have characterized a variety of SiC devices (first- and second-generation 1200 V SiC MOSFETs and 1200 V SiC JFETs) with regards to threshold voltage shifts and leakage currents at high temperatures under both static and dynamic gate bias stress conditions. It was found that, although the stability of SiC MOSFETs has increased dramatically from the first- to the second-generation due to an increase in the quality of the gate oxide layer, SiC JFET devices (which lack a gate oxide altogether) are much more stable with respect to ΔVT for both types of gate bias stresses at high temperatures. We have also characterized the interface trap density (DIT) in SiC MOSFETs based solely on changes in the sub-threshold slope of the devices’ I-V curves under elevated temperature and bias stress, and have produced ∆DIT profiles showing relative changes in interfacial defect concentration at energy levels referenced to the calculated surface potential at the threshold voltage. We have found that the defect density of second-generation SiC MOSFETs is almost an order of magnitude lower than similar first-generation devices from the same manufacturer, consistent with the decreased VT shifts seen in voltage/temperature stress experiments.

Characterization of Reliability in SiC Power Devices

The low intrinsic carrier concentrations, high breakdown voltages, and high thermal conductivities of wide-bandgap semiconductors make them attractive alternatives to traditional Si-based power electronics, especially for high-temperature/power switching applications such as motor drives, hybrid electric vehicles, and photovoltaic inverters. Silicon Carbide (SiC) is an especially strong candidate to replace Si devices due to widespread availability of SiC substrates, vertical device topologies, and the ability to thermally grow a silicon dioxide (SiO2) layer on SiC to serve as a gate dielectric, similar to established Si technology.SiC MOSFETs have been commercially available for over three years with blocking voltage of 1200V and excellent on-state resistances (~80 mΩ). In addition, SiC MOSFETs may be able to operate at higher temperatures than competing Si IGBTs or MOSFETs. Currently the most significant hurdles to market penetration are reliability and cost.SiC MOSFET reliability challenges stem mainly from poor SiC/SiO2 interface quality. When operated under high gate field and temperatures, threshold voltage (VT) instabilities are often observed both in SiC MOSFET [1] and MOS capacitor [2] structures, primarily due to the large number of electrically active SiO2 bulk and SiC/SiO2 interface states [3].The application of a gate voltage (VG) may result in electron (positive VG) or hole (negative VG) injection from the SiC into the oxide, populating traps at the SiO2/SiC interface and/or within the SiO2 bulk. These populated traps alter the surface potential and shift the VT necessary to switch the device. Recent measurements on second-generation commercially available SiC MOSFETs indicate significant progress on this front compared to earlier devices, although appreciable VTshifts still exist for relatively moderate stresses (Fig. 1a).We have characterized 1200 V SiC MOSFETs as well as Junction FETs (JFETs), which do not utilize a gate oxide, at high temperatures under both static and dynamic gate bias stress conditions. SiC JFET devices demonstrate more stable VT than SiC MOSFET devices for both types of gate bias stresses at high temperatures (Fig. 1b). For static gate bias stresses, packaged JFET devices exhibited a negligible VT shift (ΔVT < 2 mV) for temperatures up to 250oC. At higher temperatures, bare JFET die demonstrated ΔVT < 10 mV up to 525oC. Further, in contrast to the SiC MOSFETs, the VTof the SiC JFETs was unaffected by dynamic gate bias stress over the test period, although the sub-threshold leakage current increased with time [4].In addition to monitoring VT shifts, we have calculated the change in density of SiC/SiO2 interface traps (ΔDIT) due to the application of gate stress to MOSFETs. These profiles can be extracted from I-V curves for SiC MOSFETs based on the changes in sub-threshold slope. This technique can either be used to determine ΔDIT (if body doping and gate capacitance are unknown) or absolute DIT at specific energies within the bandgap (if doping and capacitance are known) [5].This work was performed under the DOE Office of Electricity programs managed by Dr. Imre Gyuk. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.[1] A. J. Lelis, et al., "Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements," IEEE Trans. Electr. Dev., vol. 55 (8), pp. 1835-1840, 2008.[2] M. J. Marinella, et al., "Evidence of Negative Bias Temperature Instability in 4H-SiC Metal Oxide Semiconductor Capacitors," Appl. Phys. Lett., vol. 90 (25), pp. 253508-253508, 2007.[3] D. K. Schroder, "Progress In SiC Materials/Devices and Their Competition," Int. J. High Speed Electr. and Syst., vol. 21 (1), p. 1250009, Apr 2012.[4] J. Flicker, et al., "Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs and JFETs at High Temperatures," High Temperature Electronics Conference (HiTEC), Albuquerque, NM, 2014.[5] D. R. Hughart, et al., "Sensitivity Analysis of a New Technique for Trapped Charge Extraction in SiC MOSFETs from Subthreshold Characteristics " International Reliability Physics Symposium (IRPS), Waikoloa, HI, 2014.