Duty-cycle Correction Circuit Research Articles

Digital duty-cycle correction circuit for clock paths in radiation-tolerant high-speed wireline transmitters

Ongoing developments in the field of radiation-toleranthigh-speed transmitters (HSTs)aim at increasing the data rates above 25 Gb/s while increasingtotal ionizing dose (TID)tolerance above 1 Grad. The use of half-rate architectures imposes tight constraints on clock signal quality, in particular its duty-cycle. Radiation degradation of transistors in the clock path causesduty cycle distortion (DCD), affecting the output signal quality of the HST. In this paper, a digitally controlled duty-cycle correction circuit suitable for HST is presented. It compensates forprocess voltage temperature (PVT)variations as well as radiation-induced duty-cycle distortion of the clock.

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells are used to make the circuit power efficient. The circuit uses three 2× stages instead of an edge combiner to achieve 8× multiplication, thus requiring far less power and chip area as compared to conventional phase-locked loop (PLL) circuits. The proposed 8× multiplier occupies an active area of 0.09 mm2. The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz.

Design of duty cycle correction circuit using ASIC implementation for high speed communication

This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cycle. DCC have improved stability, correction range, and operating frequency compared with mixed-signal and all-digital DCCs. In this analysis, the duty cycle correction circuits and their significance in Application Specific Integrated Circuit (ASIC) design, along with typical implementation methods, are discussed.

A High-Frequency and Low-Jitter DLL With Quadrature Error and Duty-Cycle Corrections Based on Asynchronous Sampling

This paper presents a quadrature error and duty-cycle correction circuit based on an asynchronous sampling technique. Sampling the multi-phased clocks provides their phase and duty-cycle information, which are then utilized to compensate for the quadrature and duty-cycle errors. The intrinsic down-conversion operation of the proposed sampling approach enhances the correction accuracy by mitigating circuit mismatch effects. The quadrature-error corrector (QEC) and duty-cycle corrector (DCC) circuits receive control signals generated from the asynchronous phase detectors and correct the clock outputs accordingly. Combined with a delay-locked loop (DLL), the proposed design is fabricated in a 40-nm CMOS process, consumes 7.2 mW, and occupies 0.023 mm. It achieves 0.837-ps RMS jitter and 1.68∘ maximum phase error from multiple chip samples.

Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the settling behavior of an asynchronous sampling duty cycle corrector is limited in some operation conditions, which degrades its robustness and performance. This paper, therefore, performs analysis on the settling behavior of the asynchronous sampling in various operating conditions and proposes a control scheme to avoid the lagged settling. To verify the proposed duty cycle corrector and its analysis, a prototype design is implemented in a 40-nm CMOS process and its performance is verified by post-layout simulations. The proposed duty cycle corrector achieved very small duty cycle errors (less than 0.8%) and consumed 540 uW per one DCC unit.

Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency

This paper presents a fast locking and wide range input frequency all-digital duty cycle corrector (ADDCC). The proposed ADDCC circuit comprises a pulse generator and a clock generator. The pulse generator is edge-triggered by an input signal to produce a 0 degree and 180 degree phase. The clock generator uses a 0 degree and 180 degree phase to produce the 50% duty cycle output signal. It corrects the duty cycle of the input signal in six clock cycles. The proposed ADDCC is implemented in a 0.35 µm CMOS process. The circuit can operate from 10 MHz to 100 MHz, and accommodates a wide range of input duty cycles ranging from 30% to 70%. The duty-cycle error of the output signal is less than ±1%.

A BMC Analog and Digital PHY for USB Type-C Power Delivery

A Type-C biphase mark code (BMC) transceiver in 0.14- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology is presented. The analog PHY in combination with digital PHY supports BMC data for USB power delivery (PD) negotiations through a Type-C cable. It compensates for signal-level loss and duty cycle distortion due to ground shifting at both ends of a Type-C cable. Analog receiver includes a BMC squelch detector decision-making comparators and a duty cycle correction circuit. Analog transmitter includes a slew rate control circuit, level shifter, and linear line driver. Digital PHY makes more corrections on duty cycle in the receiver side, recovers bits and symbols from the asynchronous serial data, and sends BMC coded data to the transmitter. The connector-facing high-voltage pins to which an analog transceiver is connected are protected against the high-voltage surge. Analog receiver consumes 0.2-mA current under 3-V supply and analog transmitter consumes 1.7-mA current to drive a 1-nF and serial 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> loads. The total area of receiver and transmitter with all supporting circuits and high-voltage switches is 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The implemented transceiver is compliant with USB PD and Type-C standards with respect to all required parameters.

A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS

This paper proposes an SST-CML-Hybrid (SCH) output driver, and its corresponding hybrid-path feed-forward equalization (FFE) scheme, to enhance the energy efficiency of a PAM-4 transmitter (TX). Specifically, the SCH driver features one SST branch + one CML branch to co-synthesize the PAM-4 data, reducing substantially the signaling power, switching power and equalization power. The PAM-4 TX further integrates a half-rate serializer with 4-bit 3-tap FFE, duty-cycle correction circuits and a T-coil output matching network. Prototyped in 28-nm CMOS, the PAM-4 TX achieves a broadband return loss <−10dB up to 50 GHz, and occupies a compact die area of 0.0345 mm2. Operating at 40 Gb/s and at a 0.9-V supply, the TX dissipates 19.5 mW, of which 6.4 mW is due to the SCH driver. The corresponding energy efficiencies are 0.16 and 0.5 pJ/bit for the SCH driver and TX, respectively; both compare favorably with the prior art.

A power-efficient 14.8-GHz CMOS programmable frequency divider with quadrature outputs in 40-nm CMOS process

This paper presents a power-efficient CMOS frequency divider (FD) with wide-band programmable division ratio and quadrature outputs for high-speed data transmission applications. The proposed FD consists of a power-efficient programmable divider (PD), a complementary volt-age-to-time converter based duty-cycle correction circuit, and a compact quadrature divider (QD). In the chain of PD, a sense-amplifier based dynamic flip-flop is proposed for 2/3 divider cell to achieve high-speed operation with significantly reduced power consumption. In addition, a simple but effective QD based on two pseudo-differential voltage-controlled tri-state inverters, is beneficial for generating precise quadrature output signals. Measurement results in 40-nm CMOS process show that the proposed FD achieves a wide division range from 16 to 254 and operates up to 14.8 GHz while consuming the power of 540.6 μW at 1.1-V supply, and occupying the active area of 0.00267 mm2 (114.6 μm × 23.3 μm).

A novel technique for duty cycle correction for reference clocks in frequency synthesizers

Frequency Multipliers to be used with Frequency Synthesizers require duty cycle of nearly 50% and low phase noise contribution to the overall system phase noise for proper operation. In this paper, we first analyze the impact of the imperfect duty cycle clocks on the overall synthesizer system performance, then propose a mixed signal solution based on the fact that the average DC value of a signal is proportional to its duty cycle. The solution uses a feedback loop for coarse and fine duty cycle correction resolution. Proposed duty cycle correction circuit can correct input duty cycle variations from 40% to 60% for a 40MHz input frequency with 50%±0.3% accuracy. Furthermore, in order to estimate the output clock phase noise, a simulation method with supply white noise model is proposed. The circuit is implemented in 65nm UMC CMOS process. Operating from 1.2-V supply, the circuit only dissipates 0.26mA.

A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI

Pushed by the ever-increasing demand of high-speed connectivity, next generation 400 Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45 Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits feed-forward equalizer (FFE), and allows tuning the output impedance to ensure good source termination. Implemented in 28 nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, $>>2$ kV HBM ESD diodes, and delivers a full swing of 1.3 Vppd at 45 Gb/s, while drawing only 120 mA from 1 V supply. The power efficiency is $\sim ~2$ times better than previously reported PAM-4 transmitters.

2.5 mW 2.73 GHz non‐overlapping multi‐phase clock generator with duty‐cycle correction in 0.13 µm CMOS

A high-speed low power multi-phase clock generator with a simple duty-cycle correction circuit is presented. By adding tail transistors driven by the out-phase signal as a discharge path to correct the phase overlapping in the conventional design, 25% duty cycle multi-phase clocks are obtained with <1° phase error. Thanks to this simple topology, the proposed work is featured with fast-speed, low power with a small silicon area. Fabricated in a 0.13 µm RF CMOS process, the proposed clock generator has a measured operating frequency up to 2.73 GHz with a maximum power consumption of 2.5 mW from a 1.2 V supply.

A 800 MHz-1.1 GHz 1.2 mW Delay Locked Loop with a Closed Loop Duty Cycle Corrector

In this paper a low power delay locked loop with a closed loop duty cycle corrector is proposed. The duty cycle corrector circuit is a dual loop circuit which receives a clock signal with 30%~70% duty cycle and generates a clock signal with 50% ± 2% duty cycle. Thepowerconsumption of the overall circuit is 1.2 mW. This circuit is fabricated in 0.18 um CMOS technology. Measurement results show that the RMS jitter of the proposed work is 4 ps at 1 GHz.

Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit

A clock skew-compensation and duty-cycle correction circuit (CSADC) is used as the second-level clock distributing circuit to align a system global clock while maintaining a 50% duty cycle. A power-efficient, range-unlimited, and accuracy-enhanced CSADC, designed mainly with a new delay-interleaving and -recycling technique that mitigates operating frequency limitations while keeping overhead costs low, is proposed in this paper. Our preliminary research results prove the feasibility of the proposed technique and show that the operating frequency ranges from 110 MHz to 1.75 GHz, with the corrected duty cycle varying from 51.2% to 48.9% based on 0.18- $\mu $ m CMOS technology. Meanwhile, the lock-in time, static phase error, and power consumption are, respectively, 26 clock cycles, 4.2 ps, and 5.58 mW at 1.75 GHz.

A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications

This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured duty-cycle error for the 50% duty-rate is below 1% (or 10 pS) within 320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.

A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology

This paper presents an all digital delay-locked loop (DLL) which achieves low jitter and stable duty cycle correction (DCC) operation. Since the DLL has dual DCC circuit, with the combinations of two DCC circuits, the DLL can correct +12.9% and -6.13% duty error under 2% at 333 MHz with 1.6 V. The DLL operates up to 1.67 GHz with 1.8 V and 1.78 GHz with 2.0 V supply voltage, and its peak-to-peak jitter at 1.4 GHz with 1.8 V is 29 ps. The power dissipations are 4.2 mW (5 mW) at 100 MHz and 19.8 mW (29.5 mW) at 1 GHz with 1.5 V (1.8 V) supply voltage with the help of the update gear circuit from the previous work. And the DLL is fabricated with 54-nm DRAM CMOS technology. The active area of the DLL is 0.11 mm2.

Clock buffer with duty cycle corrector

A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10–90% for generated 50% duty cycle of output clock with error less than 0.9%. Moreover, it enhances the input clock signal driving ability and keeps the same duty cycle as input clock within range from 20% to 80% with a maximum duty error of 0.5%. The proposed circuit operation frequency range is from 100MHz to 1GHz. The proposed circuit has been fabricated in a 0.18μm CMOS technology.

A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration

A 3-8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitters at 8 GHz are 11.44 and 6.67 ps before and after calibration, respectively. The power dissipation at 8 GHz is 18 mW for a supply voltage of 1.2 V, and the measured output duty cycle variation is less than 3%.

Wide frequency range duty cycle correction circuit for DDR interface

The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500MHz to 2GHz with ±10% duty ratio error, the output duty ratio error is corrected to be less than ±1.4%. The proposed DCC circuit is designed and verified using a 0.18um CMOS technology.

Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-/spl mu/m CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a /spl Delta//spl Sigma/ modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc.