A BMC Analog and Digital PHY for USB Type-C Power Delivery

Abstract

A Type-C biphase mark code (BMC) transceiver in 0.14- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology is presented. The analog PHY in combination with digital PHY supports BMC data for USB power delivery (PD) negotiations through a Type-C cable. It compensates for signal-level loss and duty cycle distortion due to ground shifting at both ends of a Type-C cable. Analog receiver includes a BMC squelch detector decision-making comparators and a duty cycle correction circuit. Analog transmitter includes a slew rate control circuit, level shifter, and linear line driver. Digital PHY makes more corrections on duty cycle in the receiver side, recovers bits and symbols from the asynchronous serial data, and sends BMC coded data to the transmitter. The connector-facing high-voltage pins to which an analog transceiver is connected are protected against the high-voltage surge. Analog receiver consumes 0.2-mA current under 3-V supply and analog transmitter consumes 1.7-mA current to drive a 1-nF and serial 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> loads. The total area of receiver and transmitter with all supporting circuits and high-voltage switches is 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The implemented transceiver is compliant with USB PD and Type-C standards with respect to all required parameters.