We propose a new transistor process called the Damascene gate process, where in a gate electrode is patterned by chemical mechanical polishing (CMP). In this process, source/drain implants are carried out by using a dummy gate pattern as a mask and activation annealing is completed before the actual gate oxide formation. After removal of the dummy gate, fresh oxide and gate electrode films are formed in grooves and the gate electrode film is patterned by CMP. As a result, the gate electrode surface is completely planarized and the sheet resistivity of the gate electrode is very uniform in a line width range from 0.2 µm to 5 µm. Metal-oxide-semiconductor-field-effect-transistors (MOSFETs) formed by the Damascene gate process were found to show higher electron mobility, smaller threshold voltage deviation and lower subthreshold swing due to lower surface state density as compared with conventional transistors. Therefore, the Damascene gate process is promising for the fabrication of sub-quarter-micron MOSFETs.