Dual Voltage Research Articles

Sensorless Control of IPMSM in Zero- and Low-Speed Regions Using Dual Random High-Frequency Square-Wave Voltage Injection to Reduce Audible Noise

Sensorless Control of IPMSM in Zero- and Low-Speed Regions Using Dual Random High-Frequency Square-Wave Voltage Injection to Reduce Audible Noise

Design and analysis of low power sense amplifier for static random access memory

<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>

Artificial synapse based on low-voltage Ni-doped CuI thin-film transistors for neuromorphic application

Inspired by the human brain's capacity as a powerful biological computer capable of simultaneously processing a vast array of cognitive tasks, many emerging artificial synapse devices have been developed in recent years. Electric-double-layer (EDL) transistors based on interfacial ion-modulation have attracted widespread attention for simulating synaptic plasticity and neural functions. Here, low-voltage EDL p-type thin-film transistors (TFTs) are fabricated on glass substrates, with Ni-doped cuprous iodide (Ni0.06Cu0.94I) as the channel and chitosan as the dielectric. The electrical performance of the Ni0.06Cu0.94I TFTs is investigated: current on/off ratio of 6.4 × 104, subthreshold swing of 33 mV/dec, threshold voltage of 1.38 V, operating voltage of 2 V, and saturation field-effect mobility of 15.75 cm2 V−1 s−1. A dual in-plane gate OR logic operation is demonstrated. Importantly, by applying single voltage pulses, dual voltage pulses, and multiple voltage pulses to the gate, the Ni0.06Cu0.94I transistors exhibited typical synaptic characteristics, including short-term potentiation, short-term depression, long-term potentiation, long-term depression, paired-pulse facilitation, and spiking-rate-dependent plasticity. Furthermore, the synaptic transistor can also simulate the learning–forgetting–relearning process of the human brain. These remarkable behaviors of voltage-stimulated synaptic transistors have potential for neuromorphic applications in future artificial systems.

An improved modulation algorithm for the dual‐output six‐switch inverter with reduced switching frequency

AbstractThe six‐switch inverter has gained significant attention due to its ability to achieve dual AC voltage outputs with fewer semiconductor power devices. However, with existing pulse width modulation (PWM) algorithms, the switching frequency of the two middle‐position power devices is twice that of the other four power devices at the upper and lower ends. Therefore, this paper proposes an improved PWM algorithm for the six‐switch converter based on the unipolar modulation principle. The proposed algorithm can significantly reduce the switching frequency of the two middle‐position power devices. Research results indicate that, under optimal conditions, the switching frequency of the two middle‐position power devices is as low as the frequency of the AC output voltages, and in the worst‐case scenario, it is only half the carrier frequency. Consequently, the efficiency of the inverter is effectively improved. Additionally, analysis results suggest that, given the same switching frequencies of power devices, the modulation algorithm proposed in this paper for controlling the converter also results in lower Total Harmonic Distortion (THD) for the output voltages compared to traditional modulation algorithms.

Empagliflozin rescues pro-arrhythmic and Ca2+ homeostatic effects of transverse aortic constriction in intact murine hearts

We explored physiological effects of the sodium-glucose co-transporter-2 inhibitor empagliflozin on intact experimentally hypertrophic murine hearts following transverse aortic constriction (TAC). Postoperative drug (2–6 weeks) challenge resulted in reduced late Na+ currents, and increased phosphorylated (p-)CaMK-II and Nav1.5 but not total (t)-CaMK-II, and Na+/Ca2+ exchanger expression, confirming previous cardiomyocyte-level reports. It rescued TAC-induced reductions in echocardiographic ejection fraction and fractional shortening, and diastolic anterior and posterior wall thickening. Dual voltage- and Ca2+-optical mapping of Langendorff-perfused hearts demonstrated that empagliflozin rescued TAC-induced increases in action potential durations at 80% recovery (APD80), Ca2+ transient peak signals and durations at 80% recovery (CaTD80), times to peak Ca2+ (TTP100) and Ca2+ decay constants (Decay30–90) during regular 10-Hz stimulation, and Ca2+ transient alternans with shortening cycle length. Isoproterenol shortened APD80 in sham-operated and TAC-only hearts, shortening CaTD80 and Decay30–90 but sparing TTP100 and Ca2+ transient alternans in all groups. All groups showed similar APD80, and TAC-only hearts showed greater CaTD80, heterogeneities following isoproterenol challenge. Empagliflozin abolished or reduced ventricular tachycardia and premature ventricular contractions and associated re-entrant conduction patterns, in isoproterenol-challenged TAC-operated hearts following successive burst pacing episodes. Empagliflozin thus rescues TAC-induced ventricular hypertrophy and systolic functional, Ca2+ homeostatic, and pro-arrhythmogenic changes in intact hearts.

Dual polarity open circuit voltage in triboelectric nanogenerators originated from two states series impedance

Experimental and simulation studies demonstrated that the initial voltage setting significantly influences the open-circuit voltage (VOC) in triboelectric nanogenerators (TENGs). Utilizing diode configurations, we consistently observed two distinct VOCs independent of the initial settings. A lower VOC corresponded to the surface voltage (VSurface), while a higher VOC was amplified by the product of the VSurface and the TENG's characteristic impedance ratio. Notably, a lower measurement system capacitance provided a more precise representation of the inherent characteristics of the TENG. Conversely, an increase in system impedance led to a convergence of the two VOCs and a reduction in their magnitudes relative to VSurface. These findings suggest that optimizing the initial/repeated charge balancing and minimizing capacitive loads are crucial for maximizing TENG output power in practical applications.

Wireless Charging System With Dual Switchable Constant Voltage and Constant Current Outputs Based on Intermediate Coils

Wireless Charging System With Dual Switchable Constant Voltage and Constant Current Outputs Based on Intermediate Coils

Energy injection adaptive technology for wireless power transmission based on parameter identification

AbstractThis paper presents an innovative adaptive strategy implemented in wireless power transmission (WPT) systems to overcome efficiency challenges due to coupling structure misalignment and load variability. A novel versatile transmitter, capable of alternating between single and dual voltage source states via two MOSFETs has been designed. Initially, the system operates in a single voltage source mode, mutual inductance and load characteristics are pinpointed using a particle swarm optimization algorithm. Subsequently, the system transitions to dual voltage source mode, where it fine‐tunes the auxiliary voltage source's amplitude and phase based on the determined mutual inductance and load values to realize zero phase angle for optimal impedance matching. The experimental results show that this method can obviously improve the output power of WPT system. This method stands out for its simplicity, adaptability and rapid response, suggesting its potential for practical use in dynamic charging applications.

47‐1: Invited Paper: A 6Gbps Intra‐Panel Interface with Video Image Compression for Next Generation Displays

This paper proposes a 6Gbps receiver for 8K 240Hz OLED display. In the proposed receiver, video image compression is presented to double the effective data bandwidth. In addition, it proposes dual path CTLE offset voltage calibration and CTLE adaptation with eye margin tester to implement 6Gbps receiver. The prototype IC is implemented in a 0.18μm HVCMOS process and is evaluated as an 8K 65‐inch panel.

A new topology of non-isolated AC-DC quadratic boost converter with enhanced power traits

A novel AC-DC quadratic boost converter (QBC) topology is presented in this paper which can provide higher power factor (PF), lower total harmonic distortion (THD) and higher voltage when compared to a conventional AC-DC boost convertero This is achieved by using additional switched capacitor and switched inductor in the power processing stage. The presented converter is analyzed theoretically, and a voltage gain equation is derived. A simulation model is created to evaluate the converter performance under various duty cycles, switching frequency, and changing output load. The input PF, THD, and voltage gain of the simulated model were compared with conventional converter to determine the validity of the suggested converter circuit. The results show that the efficiency, PF, THD and voltage gain value reaches approximately 97.9%, 0.98, 16.14, and 2.83 respectively at a duty cycle of 50% with fixed output load of 100 Ω. A dual loop voltage and current controller is also arrayed with the proposed circuit which allows further enhancement in PF (0.997) and THD (7.45%). This converter can be a suitable option for systems where isolation is not necessary but high PF, high voltage gain and low THD are required.

Inkjet Printing Photoresist with Ultralow Viscosity on Silicon Wafers for Uniform Coating.

Inkjet printing is introduced into the photoresist coating process for uniform photoresist film formation on silicon wafers with the in-house inkjet experimental prototype. The optimization of a dual negative voltage waveform is proposed to achieve stable droplet jetting for the ultralow viscosity (0.71 mPa·s) photoresist with a 1:10 dilution ratio employed in the semiconductor packaging processes. Moreover, the maximum droplet jetting velocity can reach 9.51 m/s, and the droplet volume is controlled at ∼6.5 pL with excellent droplet concentration. The uniform film of the AZ P4620 photoresist is coated on silicon wafers by quantitatively exploring and optimizing the printhead driving frequency and movement velocity utilizing the droplet deposition model and experimental analysis. Results show that the optimal inkjet parameters with 5 kHz in jetting frequency and 6 mm/s in motion velocity can obtain a film evenness index of 4.81% with the thickness of 0.945 μm, which exhibits a more uniform photoresist film than the spray coating method. The study not only expands the application of the inkjet printing technique but also offers an alternative for photoresist coating in the photolithography process.

Cx31.1 can selectively intermix with co-expressed connexins to facilitate its assembly into gap junctions.

Connexins are channel-forming proteins that function to facilitate gap junctional intercellular communication. Here, we use dual cell voltage clamp and dye transfer studies to corroborate past findings showing that Cx31.1 (encoded by GJB5) is defective in gap junction channel formation, illustrating that Cx31.1 alone does not form functional gap junction channels in connexin-deficient mammalian cells. Rather Cx31.1 transiently localizes to the secretory pathway with a subpopulation reaching the cell surface, which is rarely seen in puncta reminiscent of gap junctions. Intracellular retained Cx31.1 was subject to degradation as Cx31.1 accumulated in the presence of proteasomal inhibition, had a faster turnover when Cx43 was present and ultimately reached lysosomes. Although intracellularly retained Cx31.1 was found to interact with Cx43, this interaction did not rescue its delivery to the cell surface. Conversely, the co-expression of Cx31 dramatically rescued the assembly of Cx31.1 into gap junctions where gap junction-mediated dye transfer was enhanced. Collectively, our results indicate that the localization and functional status of Cx31.1 is altered through selective interplay with co-expressed connexins, perhaps suggesting Cx31.1 is a key regulator of intercellular signaling in keratinocytes.

Experimental test performance for a comparative evaluation of a voltage source inverter: Dual voltage source inverter

Abstract This article proposes an adaptive Kernel-Hebbian least mean square (KHLMS) controller for a dual voltage source inverter (VSI). The recommended topology consists of a distributed energy resource (DER) supported VSI called main VSI (MVSI) and split capacitor supported VSI termed as auxiliary VSI (AVSI). Both the MVSI and AVSI are used to serve the shunt compensation when DER is not integrated with MVSI. The DER scenario is considered to suppress the active power flow shortage in the utility grid. Here, optimal active power flow control (OAPFC) is managed by MVSI and shunt compensation is achieved by AVSI during DER operated mode. Hence, a dual VSI based distribution static compensator (DSTATCOM) facilitates the configuration merits such as reduction in system downtime cost, filter rating switching stress etc. Supremacy of both the neural network (NN) based controller and topology is presented by comparing VSI (called AVSI) in the context of harmonic reduction in source side, voltage balancing, power factor (PF) enhancement, better voltage regulation and OAPFC. The experimental results are obtained through field programmable gate array (FPGA) based hardware units which exhibit radical improvement in the power quality (PQ) conferring as per the international standard grid code (IEEE-519-2017).

Research on Underground 3-D Displacement Measurement Based on Convolutional Neural Networks and Dual Mutual Inductance Voltages

Research on Underground 3-D Displacement Measurement Based on Convolutional Neural Networks and Dual Mutual Inductance Voltages

Notice of Removal: Methodology for Modifying Air Insulated Distribution Substations With Dual Voltages Part 1

Notice of Removal: Methodology for Modifying Air Insulated Distribution Substations With Dual Voltages Part 1

New, Fast, High-Performance Level Shifter for Buck DC-DC Converter in 180nm CMOS Technology

To reduce power dissipation, the dual supply voltage approach is required for analog circuits in the on-chip integrated circuits. In this paper, a novel circuit of the level shifter for Buck DC-DC Converter using cross-coupled configuration is presented. The proposed work of this paper uses this level shifter to converter voltage of 1.8V to 5V at 180 nm CMOS Technology in Cadence Virtuoso Tool. The propagation delay, energy/transition, and static power were 182.42pS, 0.01 fJ/Transition, and 6 fW, respectively. The final design area is only 60.142 μm2.

CMOS High Swing and Q Boosted Dual Core Voltage Controlled Oscillator for 5G New Radio Application

This paper describes a low power, low phase noise CMOS voltage controlled oscillator (VCO) with a cascoded cross-coupled pair (XCP) configuration for high data rate 5G New Radio (5G-NR) applications. The core consists of a primary auxiliary VCO built as a negative conductance circuit to improve phase noise and a secondary core with a cascoded formation to increase output voltage swing. A switched varactor array (SVA) wideband tuner is integrated for a wide bandwidth application in a low power implementation. The dual-core VCO was designed in CMOS 130 nm technology and occupies only 1.05 mm2 of space. With a supply voltage of 1.2 V, the VCO achieved a tuning range of 32.43% from 3.45 GHz to 4.47 GHz. At 3.96 GHz carrier center frequency with 1 MHz offset, the total power consumption is 0.7 mW with a corresponding phase noise (PN) of −121.25 dBc/Hz and a Figure of Merit (FoM) of 193.25 dBc/Hz. The results are validated using Cadence Spectra RF simulations.

Advancements in Three-Phase Electric Motor Control: The Dual Voltag Motor Controller for Seamless Voltage Switching and Enhanced Efficiency

The primary objective of this research was to create, manufacture, and assess the operational efficiency of a Dual Voltage Motor Controller capable of automatically detecting the source voltage in a three-phase system and regulating the electric motor to function with either 220V or 440V AC. The resulting technology comprises a combination of magnetic contactors and a microcontroller, serving as a switching mechanism that streamlines the reconfiguration of the electric motor's twelve leads in a delta-delta configuration. This research was conducted at Guimaras State University, focusing on the development of a device aimed at eliminating the need for rewiring motor terminals when switching between 220V AC and 440V AC power sources, and vice versa. The device is designed exclusively for operation within a three-phase system and for electric motors utilizing a delta-delta configuration with twelve leads. Upon assessing the results of the technical evaluation, it was evident that the Dual Voltage Motor Controller effectively managed to switch the electric motor between 220V and 440V alternating current. Furthermore, the data revealed that the device allowed the electric motor to operate in both forward and reverse rotations, whether under low or high voltage conditions. By introducing this innovative technology, the research effectively resolved the limitations of existing motor controllers by introducing auto-detection of the source voltage and facilitating the seamless transfer of terminal connections via magnetic contactors. According to the feedback from technical experts, there is potential for expanding the device's applicability beyond delta-delta connected motors to also encompass wye-delta starting and running configurations for three-phase alternating current motors.

Highly reliable a‐Si:H gate driver on array with complementary double‐sided noise‐eliminating and dual voltage levels for TFT‐LCD applications

AbstractIn this work, we present a high‐reliability gate driver on array (GOA) for a 10.7‐in. HD (1,280 × RGB × 720) TFT‐LCD panel, featuring an alternatively double‐sided noise‐eliminating function. The gate driver circuit is designed with 12‐phase clock signals that exhibit 75% signal overlapping, threshold voltage recovering, and double‐sided driving schemes. The double‐sided driving scheme reduces the number of mental wires and TFTs in the gate driver circuit, resulting in a smaller layout area for GOA. By utilizing dual levels of voltage, we implemented a negative gate bias method to mitigate threshold voltage shifts for the noise‐eliminating and driving TFTs. This prevents the noises from clock signals effectively. The reliability test of the proposed GOA with 720 stages passed a strict testing condition (90°C and −40°C) for simulation and exhibited good performance over 800 hours at 90°C for measurement.

A Theoretical Approach in the Design of Single Frame 28 V DC and 270 V DC Dual Voltage Generator

Armored Fighting Vehicles (AFVs) generally operate with a 28 V DC electrical system. However, the demand for electrical power in AFVs has exceeded the capabilities of the existing 28V system. The additional load growth necessitates larger wire sizes, which adds extra weight and cost to the vehicle. Introducing a dual-bus architecture (28 V DC and 270 V DC) can lead to the efficient operation of the electrical system while meeting future demand. This paper presents the design of a Brushless Direct Current (BLDC) Dual Voltage Generator (DVG), which simultaneously outputs two voltages (28 V DC & 270 V DC) from a single frame across a wide operational speed range. The design process includes a detailed description of the individual stages, accompanied by analytical parameters and software-generated results. The modeling and analysis of the generator were carried out using Motorsolve design software. The obtained results are presented and thoroughly discussed in this paper.