Dual Threshold Voltage Assignment Research Articles

Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

In nano-scale CMOS technology, circuit reliability is a growing concern for complicated digital circuits due to manufacturing process variation and aging effects. In this paper, a statistical circuit optimization framework is presented to analyze and improve the lifetime reliability of digital circuits in the presence of process variation and aging degradation. The proposed framework takes advantage of a process variation- and aging-aware gate-level delay degradation model to characterize and evaluate the lifetime reliability of combinational circuits. A metric called Guardband-Aware Reliability (abbreviated as GAR) is proposed for a fair evaluation of the lifetime reliability of combinational circuits considering a guardband and timing yield specified by the designer. Then, using a criticality metric, a set of statistically critical gates is selected for being optimized in the optimization framework. As the improvement procedure, the dual-threshold voltage assignment technique is applied to the identified critical gates to enable the manufactured chip to improve the lifetime reliability in terms of low timing yield loss. Experimental results on ISCAS’85 and ISCAS’89 benchmark circuits show that our proposed framework increases the circuit reliability up to 9.93% for a 6-year lifetime imposing less than 6.9% timing yield loss.

Static Power Reduction in 32-bit Ripple Carry Adder using Dual Threshold Voltage Assignment

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, the dual-threshold technique is used to reduce leakage power in a 32-bit ripple carry adder by assigning high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path. The circuit was implemented using Cadence Virtuoso tools in 90-nm technology. The optimized layout of the ripple carry adder is designed using Cadence Virtuoso Layout Suite. Performance parameters such as total power, delay, static power and power delay product (PDP), were calculated and compared with the existing design topologies of full adder. The simulation results of the 32-bit ripple carry adder using the dual threshold voltage technique are compared with the conventional 32bit ripple carry adder with different threshold values. Results show that the dual-threshold technique is good for leakage power reduction during runtime mode. General Terms CMOS, full adder, ripple carry adder, critical-path, delay, high performance, low-power design, low voltage, power estimation, layout.

Design of experiments and integer linear programming-assisted conjugate-gradient optimisation of high-/metal-gate nano-complementary metal-oxide semiconductor static random access memory

Low-power consumption and stability in static random access memories (SRAMs) is essential for embedded applications. This study presents a novel design flow for power minimisation of nano-complementary metal-oxide semiconductor SRAMs, while maintaining stability. A 32 nm high-κ/metal-gate SRAM has been used as an example circuit. The baseline circuit is subjected to power minimisation using a dual-threshold voltage assignment based on novel combined design of experiments and integer linear programming (DOE-ILP) approach. However, this leads to a 15% reduction in the static noise margin (SNM) of the cell. The conjugate gradient optimisation overcomes this SNM degradation, while reducing the power consumption. The final SRAM design shows 86% reduction in power consumption (including leakage) and 8% increase in the SNM compared with the baseline design. The variability analysis of the optimised cell is performed by considering the effect of 12 parameters. SRAM arrays of different sizes are constructed to demonstrate the feasibility of the proposed SRAM cell. To the best of the authors’ knowledge, this is the first study which makes use of DOE-ILP and conjugate gradient method for simultaneous stability and power optimisation in high-κ/metal-gate SRAM circuits.

Process variation aware dual-V th assignment technique for low power nanoscale CMOS design

This paper presents a novel sensitivity-based, transistor-level, dual threshold voltage (V th) assignment technique for the design of low power nanoscale CMOS circuits. The proposed technique is based on the Plackett–Burman Design of Experiment method (PB-DOE) in which sensitivity of each transistor to delay variation due to change in its V th is obtained. The various paths in the circuit are categorized into process sensitive and process-insensitive paths. Transistors in the process sensitive paths are assigned a high V th to reduce the leakage power without affecting performance. The application of the proposed technique to ISCAS-85 C17 benchmark circuit shows 20% reduction in the leakage power as compared to conventional gate-level dual-V th assignment technique. Moreover, it is shown that the proposed algorithm can be easily extended to assign dual gate length circuits to achieve a further 20% reduction in the leakage power. The robustness of the proposed technique against process variations is demonstrated with extensive Monte Carlo Simulations. The versatility of the proposed approach to reduce the leakage power for a general CMOS circuit is demonstrated using a Manchester carry chain adder.

Statistical DOE–ILP based power–performance–process (P3) optimization of nano-CMOS SRAM

As technology continues to scale, maintaining important figures of merit of Static Random Access Memories (SRAMs), such as power dissipation and an acceptable Static Noise Margin (SNM), becomes increasingly challenging. In this paper, we address SRAM instability and power (leakage) dissipation in scaled-down technologies by presenting a novel design flow for simultaneous power minimization, performance maximization and process variation tolerance (P3) optimization of nano-CMOS circuits. The 45 and 32 nm technology node standard 6-Transistor (6T) and 8T SRAM cells are used as example circuits for demonstration of the effectiveness of the flow. Thereafter, the SRAM cell is subjected to a dual threshold voltage (dual- V Th ) assignment based on a novel statistical Design of Experiments–Integer Linear Programming (DOE–ILP) approach. Experimental results show 61% leakage power reduction and 13% increase in the read SNM. In addition, process variation analysis of the optimized cell is conducted considering the variability effect in twelve device parameters. To the best of the authors' knowledge, this is the first study which makes use of statistical DOE–ILP for optimization of conflicting targets of stability and power in the presence of process variations in SRAMs.

Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias

Adaptive body biasing is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constraints. Assigning individual bias control to each gate leads to severe overhead, rendering the method impractical. However, assigning a single bias control to all gates in the circuit prevents the method from compensating for intra-die variation and greatly reduces its effectiveness. In this paper, we propose a new variability-aware method that clusters gates at design time into a handful of carefully chosen independent body-bias groups, which are then individually tuned post-silicon for each die. We show that this allows us to obtain near-optimal performance and power characteristics with minimal overhead. For each gate, we generate the probability distribution of its post-silicon ideal body bias voltage using an efficient sampling method. We then use these distributions and their correlations to drive a statistically aware clustering technique. We study the physical design constraints and show how the area and wirelength overhead can be significantly limited using the proposed method. Compared with a fixed design-time based dual threshold voltage assignment method, we improve leakage power by 38%-68% while simultaneously reducing the standard deviation of delay by two to nine times.

A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits

Variability in process parameters leads to a significant parametric yield loss of high-performance ICs due to the large spread in leakage-power consumption and speed of chips. In this paper, we propose an algorithm for total power minimization under timing constraints in the presence of variability. The algorithm is formulated as a robust optimization program with a guarantee of power and timing yields, with both power and timing metrics being treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold-voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. The performance of the algorithm was evaluated on a variety of public and industrial benchmarks, with a library characterized using 70-nm Berkeley Predictive Technology Model. When compared to the deterministic optimization, the new algorithm, on average, reduces static power and total power at the 99.9th quantile by 31% and 17%, respectively, without loss of parametric yield. The run-time on the benchmarks is 30times faster than other known statistical power-minimization algorithms.

NOISE-AWARE SPLIT-PATH DOMINO LOGIC AND ITS CLOCK DELAYING SCHEME

This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han–Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.

Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic

Dynamic logic is susceptible to noise, especially in the ultra-deep submicrometer dual threshold voltage technology. When the dual threshold voltage is applied to the domino logic, noise immunity must be carefully considered since the significant subthreshold current of the low threshold voltage transistor makes the dynamic node much more susceptible to noise. In the first part of this paper, we introduce a new keeper transistor sizing method to determine the optimal keeper transistor size in terms of speed, power, and noise immunity. With the use of data obtained by presimulation, it is unnecessary to simulate all the design corners corresponding to the feasible NMOS evaluation transistor size ranges to find the optimal keeper transistor size. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all the domino logic gates. In the second part of this paper, we propose a new dual threshold voltage domino logic synthesis with the keeper transistor sizing to minimize the power consumption while meeting delay and noise constraints. With the optimal keeper transistor size determined by the proposed keeper transistor sizing method, the dual threshold voltage assignment to domino logic can be simplified to the discrete threshold voltage selection. Experimental results for ISCAS85 benchmark circuits show significant savings on leakage power and active power.

Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of a circuit by as much as 50%.