Process variation aware dual-V th assignment technique for low power nanoscale CMOS design

Abstract

This paper presents a novel sensitivity-based, transistor-level, dual threshold voltage (V th) assignment technique for the design of low power nanoscale CMOS circuits. The proposed technique is based on the Plackett–Burman Design of Experiment method (PB-DOE) in which sensitivity of each transistor to delay variation due to change in its V th is obtained. The various paths in the circuit are categorized into process sensitive and process-insensitive paths. Transistors in the process sensitive paths are assigned a high V th to reduce the leakage power without affecting performance. The application of the proposed technique to ISCAS-85 C17 benchmark circuit shows 20% reduction in the leakage power as compared to conventional gate-level dual-V th assignment technique. Moreover, it is shown that the proposed algorithm can be easily extended to assign dual gate length circuits to achieve a further 20% reduction in the leakage power. The robustness of the proposed technique against process variations is demonstrated with extensive Monte Carlo Simulations. The versatility of the proposed approach to reduce the leakage power for a general CMOS circuit is demonstrated using a Manchester carry chain adder.