Abstract
This paper presents a novel enumerative approach, with provable and efficient pruning techniques, for dual threshold voltage (V/sub t/) assignment at the transistor level. Since the use of low V/sub t/ may entail a substantial increase in leakage power, we formulate the problem as one of combined optimization for leakage-delay tradeoffs under V/sub t/ optimization and sizing. Based on an analysis of the effects of these two transforms on the delay and leakage, we justify a two-step procedure for performing this optimization. Results are presented on the ISCAS85 benchmark suite favorably comparing our approach with an existing sensitivity-based optimizer.
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