Dual-rail Logic Research Articles

An adiabatic differential logic for low-power digital systems

A new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL) is presented. ADCPL is a dual-rail logic with refatively low gate complexity. It operates from a two-phase nonoverlapping supply clock, power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed, Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50%-70% can be achieved over the static complimentary metal oxide semiconductor case within a practical operation frequency range. The results also show that the lower the operating frequency, the larger the energy savings for an ADCPL circuit.

Forward body-bias MOS (FBMOS) dual rail logic usingan adiabaticcharging technique with sub –0.6 V operation

A novel logic family for low-voltage adiabatic logic, called forward body-bias MOS (FBMOS) dual rail logic, has been proposed. This technique uses forward body-bias effects to enable non-floating output levels during the entire data valid time without increased transistor count.

Contention solver for a superconducting packet switch

The paper describes the architecture of a contention solver (CS) to be used in a superconducting packet switch prototype, and the design and tests of 2/spl times/2 switching elements which compose the CS. The contention solver is based on a Batcher sorter, in which switching elements check for contention between input packets. A priority port is used to guarantee correct operation of the sorter even if a packet is invalidated during the sorting process. A 2/spl times/2 CS switching element with 2-bit data-width was designed in dual-rail logic. It was fabricated using three-junction SQUID gates by a standard Nb tri-layer process, and consists of 102 OR-equivalent gates in an area of 1.2 mm x 1.8 mm. Its correct operation was confirmed completely.

Rapid single-flux-quantum dual-rail logic for asynchronous circuits

Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer.

Pass-transistor adiabatic logic using single power-clock supply

We present a new pass-transistor adiabatic logic (PAL) that operates from a single power-clock supply and outperforms the previously reported adiabatic logic techniques in terms of its energy use. PAL is a dual-rail logic with relatively low gate complexity: a PAL gate consists of true and complementary NMOS functional blocks, and a pair of cross-coupled PMOS devices. In simulation tests using a standard 1.2 /spl mu/ CMOS technology, the circuit has been found to operate up to 160 MHz clock frequency and down to 1.5 V peak-to-peak sinusoidal power-clock supply. Operation of a 1600-stage PAL shift register fabricated in the 1.2 /spl mu/ CMOS technology has been experimentally verified.

Design and Evaluation of Adiabatic Arithmetic Units

Adiabatic design is an attractive approach to reducing energy consumption in VLSI circuits after exhausting the potential of conventional energy-saving techniques. Despite the plethora of adiabatic logic architectures that have been proposed in recent years, several practical considerations in the design of nontrivial adiabatic circuits remain largely unexplored. Moreover, it is still unclear whether adiabatic circuits of significant size and complexity can achieve substantial savings in energy dissipation over corresponding conventional designs. We recently designed several low-power arithmetic units using a dual-rail adiabatic logic design style. We also designed static CMOS versions of these units and compared their energy dissipation with their corresponding adiabatic designs. In this paper we describe our implementations, discuss architecture and logic-level issues related to our adiabatic designs, and present the findings of our empirical comparison. Our results suggest that adiabatic logic can be used for the implementation of relatively complex VLSI circuits that dissipate significantly less energy than their corresponding CMOS designs.

Positive feedback in adiabatic logic

An adiabatic logic family is presented, which makes use of a CMOS positive feedback amplifier. The gate is based on dual rail logic and a cascade of such gates only needs three power/clock lines to operate. The positive feedback amplifier ensures high noise immunity and takes part in the energy recovery process.

Solid-state integrated optical parallel dual-rail logic gate module

Based on the dual-rail logic, an optical parallel and cascadable binary logic gate is proposed, which consists of prisms for beam splitting and combining and controllable halfwave plates for customizing logic operations. All sixteen logical operations can be implemented. Electro-optic crystals are suggested as the controllable halfwave plates. A compact solid-state integrated gate module can be constructed by packaging the prisms, the crystals and the spatial light modulators.

A subnanosecond Josephson 16-bit ALU

The design and characteristics of a Nb based Josephson 16-bit arithmetic logic unit (ALU) for use as a major component of a practical Josephson microprocessor are discussed. The ALU has 900 gates and uses dual-rail logic to perform 12 functions. One of the simplest algorithms, the ripple-carry method, is used. Experiments confirmed that ALU functions operated correctly. The critical path delay time was 860 ps for a 10.1-mW power dissipation. Average values estimated from experiments are 9.2 ps for the gate delay and 113 mu W for the gate power dissipation. The results demonstrate that development of a Josephson microprocessor is feasible.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Josephson 2-bit arithmetic logic unit

A Josephson 2-bit arithmetic logic unit (ALU) is presented. A four-junction logic (4JL) gate-family is used in the ALU circuit. The ALU circuit is designed based on a dual-rail logic to perform both the arithmetic and the logic functions. The circuit was fabricated with Nb/Al-oxide/Nb tunnel junctions using a 3- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">{\mu}m</tex> minimum line width technology. For each 16 functions, the circuit was completely confirmed in consistent logic operations. The operating time was measured to be 165 ps in the arithmetic function of subtraction, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</tex> minus <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</tex> . Power dissipation was estimated to be 581 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">{\mu}W</tex> in the circuit.

High-speed unit-cell for Josephson LSI circuits using Nb/AlO&amp;lt;inf&amp;gt;x&amp;lt;/inf&amp;gt;/Nb junctions

In this paper, we will discuss the design, fabrication and evaluation of an OR gate and a unit-cell for Josephson logic LSI circuits using all niobium junctions. We fabricated the unit-cell using two Modified Variable Threshold Logic (MVTL) OR gates and one single-junction AND gate. The cell performs the logical opration (A+B).(C+D), which is the basic operation of the dual rail logic method, suitable for Josephson devices. The gates utilized Nb/AlO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> /Nb Josephson junctions with a minimum diameter of 2.5 μm, Nb wirings, Mo resistors, and SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> insulators. The cell size, complete with supply resistors, was 82 μm × 132 μm. The gate delays were measured using the Josephson sampling technique with two sampling heads. The minimum delay of the OR gate in the cell was 4.2 ps, and that of the three-fanout cell was 11.5 ps. The experimental results were consistent with calculations based on measured parameters.

Digital optical computing with one-rule cellular automata

Symbolic substitution is a parallel technique for applying pattern transformation rules to an array of ON/OFF cells. A single pattern transformation rule that requires a small fan-in and fan-out is shown to be sufficient for all computing. A simple optical architecture that makes use of optically nonlinear arrays and spaceinvariant imaging can implement the rule. Configurations of cells are arranged to realize dual-rail logic operators and connection primitives. Circuits are created by customizing a fixed 2-D mask to image light onto selected cells of the array. The presented techniques are intended to provide a foundation for work on digital optical computers.

A 280-ps Josephson 4-bitx4-bit parallel multiplier

The multiplier circuit is implement in 5-/spl mu/m Resistor Coupled Josephson Logic (RCJL) and uses dual-rail logic aiming for high-speed operation. The array configuration was adopted for its design simplicity. The circuit contains 249 gates consisting of 862 Josephson junctions. The experimental multiplier was fabricated using 5-/spl mu/m lead-alloy Josephson IC processes. The complete operation of the multiplier was confirmed to be proper, with a critical path delay of 280 ps. The total power dissipation was 1 mW. This critical path delay is one order of magnitude, and the power dissipation more than two orders of magnitude smaller than those achieved with high-speed semiconductor devices, such as GaAs field-effect transistors and silicon bipolar transistors.

A high-speed four-bit full adder with a resistor coupled Josephson logic

A four-bit full adder circuit implemented in resistor coupled Josephson logic (RCJL) has been designed and successfully tested with 173-ps critical path delay. The full adder circuit uses dual rail logic with emphasis on high-speed operation. An experimental four-bit adder circuit was fabricated using lead-alloy Josephson IC technology with a 5-µm minimum feature size and a 7-µm minimum junction diameter. The circuit consists of 80 devices with 264 junctions. The minimum critical path delay for the ripple carry adder was measured to be 173 ps/4 bits. This result demonstrates the RCJL potential for high-speed digital applications.

Variable threshold logic with superconducting quantum interferometers

This paper proposes a two-junction interferometer called Variable Threshold Logic. It has both magnetically-coupled control-lines and current-injection terminals. The threshold curve of this gate can be shifted by the applied currents. This property enables its use for both OR and AND function with the same structure by only changing the wiring. Operating margins of ±12 % for OR and ± 29 % for AND are obtained with the optimized device parameters. Any logic circuit can be obtained by Josephson master-slice LSI of this gate with a dual-rail logic system.