Dual Port Research Articles

Verification of Dual Port RAM using System Verilog and UVM: A Review

Verification of Dual Port RAM using System Verilog and UVM: A Review

A novel square fractal dual port MIMO antenna with tri band rejection capabilities

A novel two port edge chamfered square fractal MIMO antenna incorporating triple band rejection characteristics is designed and investigated in this article. Defected ground structure and metamaterial is incorporated at the ground plane of the antenna to create triple band notch behavior. To minimize the mutual coupling a meta material structure is utilized in the ground. Further to create MIMO structure and to enhance the performance metrics of the antenna two identical antennas are kept side by side. The proposed antenna exhibits an impedance band width from 2.35 to 9.04 GHz and it holds a size of mm 65 mm × 35 mm × and 1.6 mm. Which is compact in size. To validate the results, the prototype structure is fabricated and tested. The measured results are presented along with simulated results.

Integrated DC-AC and AC-DC converter using H-converter for wide range voltage applications

PurposeThis paper aims to propose Hidden Converter (H-Converter) combined with dual port 3Ø inverter for energy storage application to produce wide range of voltage. Some of the application required wide range of voltages, but problem from E-chopper is either boost or buck mode of operations, both modes are not possible. To overcome this drawback, H-Converter is combined with dual port 3Ø inverter controlled by carrier-based pulse width modulation (CB-PWM) technique is added with zero sequence injection.Design/methodology/approachHidden converter is a bidirectional DC-DC chopper used to convert fixed DC to variable DC and vice versa in both buck and boost modes of operations. Dual port inverter is combined with hidden DC-DC converter can produce wide range of voltages.FindingsThe bidirectional DC-AC converter requires less power for processing and consumes less power losses by using modest carrier built- pulse width modulation scheme through proposed zero structure addition.Originality/valueBy using this proposed strategy H-Converter can produce wide range of voltage in both the sides and mostly power is processed in the 3Ø inverter with a one stage conversion with less power loss. As a result, with one stage power conversion has more efficiency because of less power loss. This proposed converter has designed by analysis, and the real time result is tested in an experiment.

Efficient Transition Hybrid Two-Layer Feed Network: Polarization Diversity in a Satellite Transceiver Array Antenna

In this article, an efficient solution for the development of a new class of two-layer microstrip patch antenna (MPA) with orthogonal polarization ports, based on substrate-integrated waveguide (SIW) through an aperture coupling technique, is presented. Applying the SIW feeding network and aperture coupling to feed the MPA reduces the losses resulting from the feeding circuit and gives a more compact and efficient system. The proposed 4 × 4 array consists of two stacked layers, including an SIW layer as a feeding network and one layer as an antenna layer. The main design feature is the dual orthogonal port to generate different linear polarizations (LPs) (horizontal, vertical, 45°, and 135°). Each layer can be easily fabricated by a single layered printed circuit board (PCB) technology, and then PCB laminates are fixed together using screws. The measured -10-dB impedance bandwidth spans from 9.25 to 10.2 GHz (9.76%). The maximum measured gain at 9.9 GHz is 18.2 dB. The peak radiation efficiency is 84%. The proposed dual orthogonal port antenna exhibits low cost, ease of design, lightweight, high efficiency, and compactness, which makes it a suitable candidate for the polarization diversity in a transceiver for Earth-station applications.

On the optimal design of sliding rotary vane pump for heavy-duty engine cooling systems

Presently the on-the-road transportation sector is responsible of the 21% of the whole CO2 amount emitted into atmosphere. This pushes the International Governments and Organizations to provide strict limitations in terms of ICEs emissions, also introducing fees payment for the car manufacturers. The vehicle electrification allows certainly to meet these requirements, but the higher cost and the need of a green electricity still limit a widespread diffusion among all social classes. Thus, the technological improvement of internal combustion engine plays a key role in the transition period. Among these technologies, the engine thermal management allows to achieve a good compromise between the CO2 emission reduction and related costs. It was demonstrated that replacing the conventional centrifugal pump of engine cooling system with a sliding vane rotary pump (SVRP), important benefits in terms of CO2 emission reduction can be achieved as centrifugal pump efficiency decreases significantly when the engine works far from the maximum load (i.e. design point of the pump). Nevertheless, the complex thermo-fluid-dynamic phenomena taking place inside a SVRP make its design not immediate, particularly if heavy duty ICE cooling systems are considered. These applications indeed are challenging due to the wide operating range and the huge flow rates which pump must deliver. These operating requirements make difficult the choice of the main design parameters: among the different ones, the pump revolution speed and displaced volume. In the present paper a design strategy is developed for this type of pumps based on a comprehensive mathematical model of the processes occurring, predicting volumetric, indicated and mechanical efficiencies. The model was validated with a wide experimental activity so acting as virtual development platform. The results show how the best global efficiency (0.59) is achieved adopting a dual axial intake port configuration, with a suitable choice result of a trade-off between displaced volume and revolution speed. The analysis also show that the pump keeps its efficiency close to the design one for a wide operating range which is particularly suitable for the cooling of an ICE.

Effect of a dual air inlet port of the 4-valve CI engine on the swirl flow generated at the bottom region of the cylinder using the PIV technique

The in-cylinder flow in diesel engines significantly affects fuel-air mixing, combustion, and emissions. The present study investigates how engine properties such as the engine speed and intake port affect the swirl flow of a single cylinder diesel engine. Using the obtained velocity data, the strength of the swirl flow was calculated and represented by swirl ratio. It is observed from experiments that, the swirl flow of a diesel engine is affected by changing the engine speed and the area of the intake port, in which the center position of the swirl flow was identified during intake and compression strokes. Besides, the in-cylinder flow is also affected by the opening area of the helical port such that when the opening increases, the center of swirl flow moves away from the center of cavity and the swirl ratio becomes smaller. Furthermore, by reducing the aperture of the helical port a more stable swirl was acquired. The obtained experimental results revealed that, the tangential port which generates a large-scale intake flow interacted with the small-scale swirl flow generated by the highly tilted helical port. Additionally, the inflow created by the helical port disturbed the swirl flow generated by the tangential port. The results also illustrated that the tangential port showed a higher amount of turbulent kinetic energy inside the piston concavity. In addition, tangential port leads the turbulent kinetic energy toward the outer periphery and helical port resulted to the inner side of piston concavity.

Electronically Reconfigurable WLAN Band-Notched MIMO Antenna for Ultra-wideband Applications

A low-profile electronically reconfigurable WLAN band-notched dual port multiple-input multipleoutput (MIMO) antenna design for ultra-wideband applications has been presented. Antenna elements exhibit good impedance match (S11 ≤ -10 dB) over entire ultrawideband (3.1 to 10.6 GHz) spectrum. The decoupling structure is used to improve isolation (S12/S21) above 20 dB over entire UWB band. Moreover, reconfigurable band-notching is achieved by inserting PIN diodes along the inverted L-shaped slots, in each radiator. Notch at WLAN (5.5 GHz) frequency band is achieved by switching the PIN diode to ‘OFF’ state. The antenna design is fabricated as well as measured, and the results suggests that the proposed design with switchable WLAN band-notch characteristics is suitable candidate for ultra-wideband applications.

Dual-Polarized Wearable Antenna/Rectenna for Full-Duplex and MIMO Simultaneous Wireless Information and Power Transfer (SWIPT)

Owing to the mobility of a wearable antenna and the unpredictable body-centric communications environment, dual-polarization antennas are essential for both communications and energy harvesting. This paper presents a dual-polarized four-port textile antenna/rectenna for wearable simultaneous wireless information and power transfer (SWIPT) applications. The proposed antenna utilizes dual ports for both off-body communication and energy harvesting from horizontal and vertical polarizations. The antenna maintains a 100 MHz bandwidth with an S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> under -10 dB around 2.4 GHz in the presence and absence of the human body, and at least 10 dB small-signal and large-signal isolation between all ports. The antenna maintains a 70-88% measured total efficiency and 8.4-9.6 dBi gain for various on-phantom positions across both communication ports. The measured mutual coupling is under -10 dB between co-polarized rectenna/antenna ports, and under -16 dB between orthogonally-polarized ports. A high RF to DC peak power conversion efficiency of over 70% (±5%) is achieved with a broadside harvesting pattern. Based on the proposed antenna's performance, SWIPT microstrip antennas can be adopted for both full-duplex and MIMO applications, significantly reducing the complexity of future battery-free networks for both wearable and non-wearable applications.

Dual port mach-zehnder modulator in fiber-optic transmission lines of radio frequency signals

Dual port mach-zehnder modulator in fiber-optic transmission lines of radio frequency signals

Attitude Output of Strapdown Inertial Navigation System Based on Laser Gyro

Aiming at the real-time problems of signal acquisition, attitude calculation and data exchange of strapdown inertial navigation system, the data exchange between the core device of three-axis screw instrument and three-axis accelerometer sensor inertial unit (IMU) is analyzed. The RS-232 serial interface and can bus interface are adopted, which can not meet the requirements of high-speed sampling and real-time data transmission of each sensor. A new method based on FPGA dual port RAM and dual DSP is proposed Speed data access mode, through the main control CPU clock synchronization, can effectively solve the bottleneck problem of data communication between IMU attitude data and core equipment, and realize the rapid response ability of vehicle navigation system. Experiments and simulations show that the highest frequency attitude update rate of the method can reach 2000kHz, which can effectively solve the input and output data and navigation calculation ability, and improve the maneuverability of the carrier.

Dual-Electric-Port Bidirectional Flux-Modulated Switched Reluctance Machine Drive With Multiple Charging Functions for Electric Vehicle Applications

This article proposes a simplified dual-electric-port drive for a flux-modulated switched reluctance machine (SRM) with flexible charging capability for electric vehicle applications. In the driving mode, the developed flux modulation control can be achieved by directly employing the modular three-leg converter compared to the conventional open-winding topology. The zero-sequence current excitation can be flexibly controlled between the dual port and the number of power switches is also significantly reduced. The corresponding carrier-based pulsewidth modulation method and harmonic current suppression strategy are both developed to improve the machine performance. In the standstill condition, flexible battery charging can be easily achieved by the drive circuit, including both the dc and ac charging, without using any additional passive components and power devices. Then, the current distribution control scheme and power factor correction strategy are further developed for the dc and ac charging, respectively. Compared with existing drive topologies, advanced flux-modulated control and flexible energy control both can be achieved with machine performance improvement and drive cost reduction. Experiments are carried out on a three-phase 12/8 SRM prototype to verify the effectiveness of the proposed SRM drive and control strategies.

Research on big data storage and compression method for dual core intelligent meter

With the rapid integration and development of cloud computing, big data and smart grid, not only the type and accuracy requirements of the collected data are increasing, but also the storage depth is getting higher and higher. In hardware, the dual port RAM design is used to improve the real-time performance of reading and writing, digital filter is used for preprocessing in software, and “Equivalent Normalization (EN)” is used to improve storage depth. These schemes save hardware storage space and improve data transmission efficiency in practical application. So the advantages of dual-core intelligent power meter will be further exploited and brought into play.

Dual Port 8T SRAM Cell Using FinFET &amp; CMOS Logic for Leakage Reduction and Enhanced Read &amp; Write Stability

Static Random-Access Memory cells with ultralow leakage and superior stability are the primary choice of embedded memories in contemporary smart devices. This paper presents a novel 8T SRAM cell with reduced leakage and improved stability. The proposed SRAM cell uses a stacking effect to reduce leakage and transmission gate as an access transistor to enhance stability. The performance of the proposed 8T SRAM cell with a stacked transistor has been analyzed based on the power consumption and static noise margin (RSNM, HSNM, and WSNM). The power consumption in the case of FinFET based 8T cell is found to be 572 pW at 22 nm technology node, which is reduced by a factor nearly as compared to that of CMOS based 8T cell. Further, in the case of FinFET based novel 8T SRAM cell at 22 nm technology node, the power consumption is found to be reduced by a factor of as compared to that of FinFET based conventional 6T SRAM cell. WSNM, HSNM, and RSNM of the 8T SRAM cell designed with FinFET logic are observed as 240 mV, 370 mV, and 120 mV respectively at 0.9 V supply voltage. When comparing with conventional 6T FinFET Cell, the proposed Cell shows 20%, 5.11%, and 7% improvement in WSNM, HSNM, and RSNM, respectively. The sensitivity of SNM with temperature variation is also analyzed and reported. Further, the results obtained confirm the robustness of the proposed SRAM cells as compared to several recent works.

Triggerless charge measurement system for fast characterization with APDs and PMTs

Particle detectors based on the response of sensitive material (plastic scintillator, saturated gas, etc.) usually need characterization and test procedures before final installation. Cosmic ray particles are normally used to perform those preliminary tests which includes a detailed inspection of the readout electronics and a data acquisition to obtain a charge distribution of cosmic ray detection.The Data Processing Interface is implemented in an FPGA (ALTERA family), designed to test the acquisition of digitized signals from light sensors, fotomultipliers (PMTs) and Avalanche photodiodes (APDs) are the most common ones. The architecture is based on a medium density FPGA that continuously reads the data coming from a 10-bit, 40MHz ADC. Input data is stored in a dual port memory designed to search for valid pulses and compress them by removing data below a programmable voltage threshold. The Interface can produce two types of data packets, non-Zero packets and empty packets. Data in non-zero packets are compressed with a lossless technique and they are marked with a start of data, time stamp, valid data and data size information for reconstruction purposes. Empty events are generated when the maximum waiting time for a valid pulse is exceeded and information is added to preserve the time continuity.

Design of Port Communication Signal Management System Based on ZigBee

Huang, K. and Sun, B., 2020. Design of port communication signal management system based on ZigBee. In: Yang, Y.; Mi, C.; Zhao, L., and Lam, S. (eds.), Global Topics and New Trends in Coastal Research: Port, Coastal and Ocean Engineering. Journal of Coastal Research, Special Issue No. 103, pp. 735–738. Coconut Creek (Florida), ISSN 0749-0208.In view of the long management time of traditional management system, the design of port communication signal management system based on ZigBee is proposed. With the support of the overall structure of the system, the IMU signal communication interface is designed and transmitted to the serial port of 77e58 through RS-422 to complete the receiving of IMU signal. Using the dual port RAM chip idt7130, it is convenient for the microcontroller 77e58 and the host pci04 to read and write the memory space. Pci04 and CPLD digital logic are designed to realize 1 MHz clock frequency division of the two processes. Research the program development interface, define the correlation coefficient in the real number field, and complete the management system design by designing the microcontroller serial port to interrupt the program flow. The experimental results show that the system consumes less management time and provides a guarantee for the stable transmission of communication signals.

High Performance Approximate Memories for Image Processing Applications

Efficient utilization of on-chip Static Random Access Memory (SRAM) space is more important on processor core design in modern Field Programmable Gate Array (FPGA) based Digital Signal Processing (DSP) applications. In the proposed High-performance Approximate Single Port (HASP) SRAM architecture, a significant amount of data is stored to achieve high performance. The constraints involved with high performance are counterbalanced to provide high accuracy, high speed, low power and area efficiency. In the proposed High-performance Approximate Sub-Bank Dual Port (HASBDP1 and HASBDP2) memory architectures, HASP has been employed and modified to work as a True DP SRAM with energy and area efficiency. The performance of the proposed memories is investigated by comparing its speed, area and power with those of the existing approaches. The proposed HASP SRAM provides 14.99% less power consumption and thirteen numbers of logic elements savings in the resource utilization than the existing conventional SP SRAM. By considering the design metrics, the proposed HASBDP SRAMs outperform than the conventional TDP and sub-bank DP SRAMs approaches. The proposed HASBDP2 exhibits 29.09%, 22.37% higher PSNR and 32.94%, 28.48% higher SSIM than the truncated least significant bit and static segment on-chip approximate memories respectively.

Parallel personal measurements of diesel engine exhaust and crystalline silica using dual sampling port

Diesel engine exhaust (DEE) and crystalline silica exposures occur simultaneously in the mining industry, and occupational sampling campaigns can be time- and cost-consuming. The authors evaluated a dual-port system for simultaneous sampling of DEE and crystalline silica in laboratory and field conditions. Laboratory tests evaluated the operation of pumps during 8 h sampling and the intensity of the flow variation for various filter loading conditions and for different modes of operation. Field validation was performed in an underground mine. Pumps operated in constant flow or constant pressure modes. Tests in constant flow mode showed that when the flowrate increased on one side of the system, it decreased on the opposite side according to the loading intensity. Tests in constant pressure mode showed that flowrates systematically decreased when using loaded cassettes. However, the higher the backpressure setting, the lower the flow variation was. Flow variations during field tests were generally within the acceptable ±5% range. However, significant flow variations were identified in higher concentrations. A significant negative correlation was found between flowrate variation and total carbon concentration. While the majority of tests support the use of the dual-port for evaluating concomitant exposures, results highlight the possibility of filter overloading as a cause of flowrate changes.

Efficient Design of Control Logic Block in Dual Port Memory

A dual port memory in QCA is a study of data in different ports, but the data conflicts are very difficult to identify. Dual port memory is mainly focused on the data priority. It can be generated from the design of the control logic block. Priority bit are used, where both ports access the same memory location. Dual port memory functionality can be identified with a priority bit. When the port having the same memory location, only the port having the high priority is selected and other port are discarded. But when the read operation are requested to both the ports at same locations, having no conflicts and both the ports are requested to perform read operations. Data conflicts on the SRAM cell can be overcome by discarding the lower priority completely. Priorities are defined in terms of the area and delay. The idea behind this work is to minimize the area and delay in the dual port memory and proposed a multilayer Cross-Over design to provide an efficiency to the dual port memory and simulation result of design are shown in QCA Designer Tool-2.0.

Multibillion packet lookup for next generation networks

Fast Internet Protocol Version 4 (IPv4) lookup is one of the key challenges that have always been faced with growing internet speed. Next generation networks promise hundreds of gigabit communication bandwidths. To support such high data rates, core networking devices require very fast IPv4 lookup for incoming packets to sustain their functionality. Researchers from academia and industry have contributed widely towards this problem, presenting numerous techniques and algorithms to improve lookup times. In this paper, a bit vector-based IP lookup engine is presented that implements parallel units to achieve 4.3 Billion Packets Per Second (BPPS) lookup speeds for 5 fields. Implementations are done using dual port Distributed RAM (DRAM) on state-of-the-art Xilinx Virtex 7 series Field Programmable Gate Arrays (FPGA). Post place and route results for different configurations showed that the proposed design consumes much less memory, facilitating multiple engines on a single chip whilst maintaining a very low overall power profile.

A dual-intake-port technology as a design option for a Sliding Vane Rotary Expander of small-scale ORC-based power units

Volumetric machines are the most suitable candidates to be used as expander in power units based on the Organic Rankine Cycle (ORC) thermodynamic concept, for waste heat recovery of Internal Combustion Engine in the on-the-road transportation sector. In particular, the technology of the Sliding Rotary Vane Expander (SRVE) shows intrinsic advantages thanks to their lower cost, shaping features, easier manufacturing and reliability and, generally speaking, very suitable operative conditions. Nevertheless, they show some disadvantages which are typical of volumetric machines, such as low capacity, limited expansion ratio and power lost by friction.Among the different technologies available to reduce the effects of these aspects (revolution speed increase, elliptical stators or with more complex geometries, tip blade optimization, rolling stators, etc.), the Dual-Intake Port (DIP) was assessed as a promising solution to enhance SVREs performance and operability. However, dual-intake port was still not conceived as design option.In this paper, a novel Sliding Vane Rotary Expander design concept involving a Dual Intake Port expander (DIP) option was developed and compared to the conventional Single Intake Port (SIP) one, under the same operating conditions. Thus, after an experimental comparison between SIP and DIP expanders, under the same conditions of mass flowrate, a theoretical expander model of the latter was validated on a set of experimental results. The model allows to outline the advantages of considering the dual port as a design option: for a specific flow rate and revolution speed, this option allows to reduce the friction losses, which represent a weak point of this volumetric machine. For a given mass flow rate of the working fluid, an additional feature is that it allows a sensible downsizing with respect to the SIP, with an axial dimension reduction up to 50%, ensuring additional weight and space saving. Despite the reduction of the dimensions, DIP produces a comparable mechanical power with respect to SIP, limiting the reduction to 8–10% of the SIP one with a 50% lower mechanical power loss due to friction. For the same flow rate, the added intake port determines a decrease of the intake pressure which is completely beneficial in terms of operating conditions of the overall recovery unit.