Dual-port Memory Research Articles

Optimized Design of Direct Digital Frequency Synthesizer Based on Hermite Interpolation

To address the issue of suboptimal spectral purity in Direct Digital Frequency Synthesis (DDFS) within resource-constrained environments, this paper proposes an optimized DDFS technique based on cubic Hermite interpolation. Initially, a DDFS hardware architecture is implemented on a Field-Programmable Gate Array (FPGA); subsequently, essential interpolation parameters are extracted by combining the derivative relations of sine and cosine functions with a dual-port Read-Only Memory (ROM) structure using the cubic Hermite interpolation method to reconstruct high-fidelity target waveforms. This approach effectively mitigates spurious issues caused by amplitude quantization during the DDFS digitalization process while reducing data node storage units. Moreover, this paper introduces single-quadrant ROM compression technology to further diminish the required storage space. Experimental results indicate that, compared to traditional DDFS methods, the optimization scheme proposed in this work achieves a ROM resource compression ratio of 1792:1 and a 14-bit output Spurious-Free Dynamic Range (SFDR) of −88.134 dBc, effectively enhancing amplitude quantization precision and significantly lowering spurious levels. This significantly improves amplitude quantization precision and reduces spurious levels. The proposed scheme demonstrates notable advantages in both spectral performance and resource utilization efficiency, making it highly suitable for resource-constrained embedded systems and high-performance applications such as radar and communication systems.

Configurable in-memory computing architecture based on dual-port SRAM

In the emerging field of in-memory computing (IMC), this study proposes a dual-port static random access memory (SRAM) IMC architecture with the distinct capability of realizing XOR encryption (XORE), thus serving as a potential solution for the Von Neumann bottleneck. Beyond providing traditional SRAM read and write operations, the proposed architecture carries out additional tasks such as multi-bit multiply and accumulate (MAC) and XOR accumulation (XORA). The architecture was simulated using a 28-nm Complementary Metal Oxide Semiconductor Process, demonstrating a minor standard deviation of 9.41 mV in bit line voltage at the SS process corner, as evidenced by Monte Carlo simulation. Energy expenditure for the MAC, XORA, and XORE, was found to be 1.65, 1.46, and 9.02 fJ/ops respectively at the TT process corner. Furthermore, the presented architecture showed considerable energy efficiency, with MAC, XORA, and XORE operations achieving energy efficiency values of 604.9, 682.7, and 110.8 TOPS/W respectively, at a supply voltage of 0.9 V at the TT process corner.

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability.

Dual-port ferroelectric NAND flash memory for large memory window, QLC programmable and disturbance-free operations

Dual-port ferroelectric NAND flash memory for large memory window, QLC programmable and disturbance-free operations

Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators

Image processing and machine learning applications benefit tremendously from hardware acceleration. Existing compilers target either FPGAs, which sacrifice power and performance for programmability, or ASICs, which become obsolete as applications change. Programmable domain-specific accelerators, such as coarse-grained reconfigurable arrays (CGRAs), have emerged as a promising middle-ground, but they have traditionally been difficult compiler targets since they use a different memory abstraction. In contrast to CPUs and GPUs, the memory hierarchies of domain-specific accelerators use push memories : memories that send input data streams to computation kernels or to higher or lower levels in the memory hierarchy and store the resulting output data streams. To address the compilation challenge caused by push memories, we propose that the representation of these memories in the compiler be altered to directly represent them by combining storage with address generation and control logic in a single structure—a unified buffer. The unified buffer abstraction enables the compiler to separate generic push memory optimizations from the mapping to specific memory implementations in the backend. This separation allows our compiler to map high-level Halide applications to different CGRA memory designs, including some with a ready-valid interface. The separation also opens the opportunity for optimizing push memory elements on reconfigurable arrays. Our optimized memory implementation, the Physical Unified Buffer, uses a wide-fetch, single-port SRAM macro with built-in address generation logic to implement a buffer with two read and two write ports. It is 18% smaller and consumes 31% less energy than a physical buffer implementation using a dual-port memory that only supports two ports. Finally, our system evaluation shows that enabling a compiler to support CGRAs leads to performance and energy benefits. Over a wide range of image processing and machine learning applications, our CGRA achieves 4.7× better runtime and 3.5× better energy-efficiency compared to an FPGA.

Research on Embedded Controller of Hydraulic Vibrating Table Based on DSP

Background: The vibration control loop is the key technology adopt to improve the control performance of the vibration table, which is set outside of the hydraulic vibration table servo control loop. However, the huge number of signal processing work prompts high demands on the calculation ability of the vibration controller. One kind of multi-CPU embedded vibration controller constructed by Digital Signal Processor (DSP) is proposed considering the working principle of the hydraulic vibration table and the Power Spectrum Density (PSD) reproduction process. The embedded controller consists of an acquisition unit, a calculation unit, and a monitoring unit distributes vibration control tasks to the different processing unit to realize distributed algorithm calculations. Every processing unit uses dual-port memory to accomplish data interaction between each other. The development of the embedded controller provides a benchmark engineering case for the design of the hydraulic vibration table vibration controller. Objective: This article focuses on the development of the multi-CPU embedded vibration controller and the distributed calculations. Meanwhile, the power spectrum density experiment is carried out to verify the performance of the hydraulic vibration embedded controller. Methods: 1) The structure of the hydraulic vibration table control system is given, that is, two closed-loop controls. The bandwidth of the system is further broadened by the vibration control of the outer loop. Besides, the accuracy of vibration control is also improved. Then, the development needs of the vibration controller are put forward according to the detailed process of the power spectrum density replication. 2) An arithmetic processing unit is formed by using TI C2000 series DSP to calculate a large number of signal processing and a signal acquisition unit at high speed. In order to improve signal processing efficiency, the signal acquisition unit is used to perform preprocessing calculations (data acquisition and filtering) and vibration control calculations in a distributed manner. 3) Processing speed is further improved by taking full advantage of DSP software sources include lots of library functions and optimized assembly library functions. 4) The friendly operation of the controller and the safety monitoring of the experiment process are realized by the industrial computer served as the human-computer interaction unit. 5) Multi-CPU data sharing is achieved through using dual-port RAM to realize. Results: Through experiments, the developed embedded controller is fully estimated. The experiment shows that the developed hydraulic vibration table can realize real-time vibration control. Concerning the acceleration power spectrum density reproduction experiment, 256 acceleration response samples are calculated, and the update time is 4ms. The tracking accuracy of the timedomain waveform is controlled within 0.3%. Conclusion: The use of the developed embedded controller with signal conditioning equipment can achieve real-time control of the hydraulic vibration table, but the performance of the embedded controller can be promoted in advance, and the performance improvement of the hydraulic vibration table embedded controller can be studied from the following aspects: 1) The Fourier calculation is executed by the acquisition unit to share the calculation workload of the calculation unit; 2) The computing unit uses a signal processor chip with better performance, although this will bring development difficulties; 3) The monitoring computer can use an embedded controller with superior performance instead of an industrial computer to reduce the size, improve the performance; 4) The DSP real-time operating system should be used, and the task scheduling of vibration control experiments should be optimized.

An alternative test method for the dual-port SRAM through the DesignWare SATA AHCI implementation in 3D IC structures

The conventional methods for testing the Dual Port Random Access Memories (DPRAM) may not be suitable for the Three-Dimensional Integrated Circuit (3D IC) structures, due to their limited test vectors with heterogeneous integration. This paper takes an Application Specific Integrated Chips (ASIC) approach to gain some insight into the Front-end behavioral testing and backend routability of the dual port memories with complex Serial Advanced Technology Attachment (Serial-ATA) design, in a 3D IC structure. The presented implementation used commercially available Dual Port memories from the two different vendors. The commercially available DesignWare Advanced Host Controller Interface (SATA/AHCI), which is based on the SATA 2.6 AHCI host and external SATA (eSATA) standard bus architecture, with My_foundry’s 14 nm low power process (14lp) technologies for the logical and physical implementations. The methodology evaluates the memory quality and performance/characteristics, in terms of timing, power and area. This paper shows memory testing in both implementation/verification in a readily built-up SATA test environment.

Designing and verification of first in first out using Verilog

Abstract: This paper deals with the designing and verification of first in first out (fifo) using verilog. A FIFO is a memory queue which controls the data flow between two modules. It has the capacity to trigger different flags according to the status of the FIFO such has empty fifo status, half read fifo status, half written fifo status, full fifo status. Both the reading and writing operation can be performed simultaneously as it has dual port memory. After the completion of designing and simulating it on xilinx vivado this report also covers the verification carried out in modelsim. A detailed discussion on the architecture of each module that is writing module, reading module and memory array along with the various test benches and waveforms of simulation and verification is included in the paper.

Design and implementation of Dual-Port Memory

Multiport memory cell using a dual-port memory cell provides required access to multi-processor-based applications. Simultaneous access can be provided using two-pass transistors, pair of bit lines, and a word line. Using specific word lines and bit lines of SRAM cell access can be provided by using dual ports memory. The single address of a memory cell can be accessed at a time during each clock pulse using single-port SRAM this drawback can be overcome by using dual-port RAM which supports concurrent read or writes access at different addresses. Efficiency is improved by using dual-port RAM. Each processor can be made to operate at different clock frequencies thereby dual-port RAM will not have any limitations of access between the two ports.

Multi-Port Memory Design in Quantum Cellular Automata Using Logical Crossing

Memory and its data communication are very significant in the Processor design and its performance. In order to attain high performance computing machine, the memory access has to be equally faster. Here in this paper, Dual port memory with Set/Reset is designed using Majority Voter in Quantum-dot Cellular Automata (QCA). Dual port memory consists of basic functional blocks such as 2 to 4 decoder, Control Logic Block (CLB), Address Checker Block (ACB), Memory Cell (MC), Data Router block and Input / Output block. These functional units are constructed using the 3-input majority voters. QCA is one of the recent technologies for nano-metric design of digital components. The functional simulation of Dual Port Memory design is verified using QCA. A novel crossover method called Logical Crossing is utilized to improve the area of the proposed design. The logical crossing does the data transmission with the support of proper Clock zone assignment. The logical crossing based QCA layouts are optimized in terms of area and number of cell counts. It is observed that 29.81%, 18.27%, 8.32%, 11.57% and 3.69% are percentage of improvement in number of cells in Decoder, ACB, CLB, Data Router and Memory Cell respectively. Also, 25.71%, 16.83%, 8.62%, 4.74% and 3.73% of improvement in area for Decoder, ACB, CLB, Data Router and Memory Cell respectively. In addition to that the proposed Dual port memory using logical crossing attains 8.26% of area and 8.65 % of number of cells improvement. Moreover, the quantum circuits of the RAM are obtained and quantum cost, constant inputs, number of gates, garbage output and total cost are estimated as 285, 67, 57, 50 and 516 respectively.

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

PurposeThis paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.Design/methodology/approachA new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.FindingsWith the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.Originality/valueThis is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

Mitigating single event upset of FPGA for the onboard bus control of satellite

This paper proposes a hybrid anti-radiation method to enhance the reliability of Field Programmable Gate Array (FPGA), which is being applied more and more in the commercial satellite. The method utilizes the advantages of Error Detection And Correction (EDAC) and Triple Modular Redundancy (TMR). Different bus control units are improved by different anti-radiation techniques. For finite state machine, dual-port Block Random Access Memory and EDAC are utilized. EDAC is also used to enhance First In First Output unit. For the simple control register, TMR is applied to improve its anti-radiation. This hybrid method can avoid the accumulated error of TMR and reduce the complexity of system. Experimental results show that the proposed method can correct 1-bit error and detect 2-bit error effectively.

Multi‐touch detector architecture based on efficient buffering of intensities and labels

This Letter presents a multi-touch detector architecture incorporating an efficient buffering scheme. Most of the power consumption in a detector is originated from the intensive use of buffers that necessitate dual-port memories. To alleviate the silicon area and the power consumption, the author scrutinises and manipulates the pattern of requests made to the buffers. More specifically, two consecutive requests are rescheduled to be processed at once, and the buffers and the surrounding circuits are modified accordingly. As a result, only one request is made to a buffer at a time, and the dual-port memories are substituted with the single-port counterparts. Implementation results demonstrate that the proposed architecture can diminish the silicon area by 36% and the power consumption by 17% compared with the state-of-the-art one.

Triggerless charge measurement system for fast characterization with APDs and PMTs

Particle detectors based on the response of sensitive material (plastic scintillator, saturated gas, etc.) usually need characterization and test procedures before final installation. Cosmic ray particles are normally used to perform those preliminary tests which includes a detailed inspection of the readout electronics and a data acquisition to obtain a charge distribution of cosmic ray detection.The Data Processing Interface is implemented in an FPGA (ALTERA family), designed to test the acquisition of digitized signals from light sensors, fotomultipliers (PMTs) and Avalanche photodiodes (APDs) are the most common ones. The architecture is based on a medium density FPGA that continuously reads the data coming from a 10-bit, 40MHz ADC. Input data is stored in a dual port memory designed to search for valid pulses and compress them by removing data below a programmable voltage threshold. The Interface can produce two types of data packets, non-Zero packets and empty packets. Data in non-zero packets are compressed with a lossless technique and they are marked with a start of data, time stamp, valid data and data size information for reconstruction purposes. Empty events are generated when the maximum waiting time for a valid pulse is exceeded and information is added to preserve the time continuity.

High Performance Approximate Memories for Image Processing Applications

Efficient utilization of on-chip Static Random Access Memory (SRAM) space is more important on processor core design in modern Field Programmable Gate Array (FPGA) based Digital Signal Processing (DSP) applications. In the proposed High-performance Approximate Single Port (HASP) SRAM architecture, a significant amount of data is stored to achieve high performance. The constraints involved with high performance are counterbalanced to provide high accuracy, high speed, low power and area efficiency. In the proposed High-performance Approximate Sub-Bank Dual Port (HASBDP1 and HASBDP2) memory architectures, HASP has been employed and modified to work as a True DP SRAM with energy and area efficiency. The performance of the proposed memories is investigated by comparing its speed, area and power with those of the existing approaches. The proposed HASP SRAM provides 14.99% less power consumption and thirteen numbers of logic elements savings in the resource utilization than the existing conventional SP SRAM. By considering the design metrics, the proposed HASBDP SRAMs outperform than the conventional TDP and sub-bank DP SRAMs approaches. The proposed HASBDP2 exhibits 29.09%, 22.37% higher PSNR and 32.94%, 28.48% higher SSIM than the truncated least significant bit and static segment on-chip approximate memories respectively.

Efficient Design of Control Logic Block in Dual Port Memory

A dual port memory in QCA is a study of data in different ports, but the data conflicts are very difficult to identify. Dual port memory is mainly focused on the data priority. It can be generated from the design of the control logic block. Priority bit are used, where both ports access the same memory location. Dual port memory functionality can be identified with a priority bit. When the port having the same memory location, only the port having the high priority is selected and other port are discarded. But when the read operation are requested to both the ports at same locations, having no conflicts and both the ports are requested to perform read operations. Data conflicts on the SRAM cell can be overcome by discarding the lower priority completely. Priorities are defined in terms of the area and delay. The idea behind this work is to minimize the area and delay in the dual port memory and proposed a multilayer Cross-Over design to provide an efficiency to the dual port memory and simulation result of design are shown in QCA Designer Tool-2.0.

Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs

With the proliferation of embedded computing, there has been a dramatic increase in utilization of FPGAs to accelerate real-time compute/data-intensive applications on embedded platforms. FPGA-based designs typically achieve high speed-performance by leveraging parallelism in computations, which require simultaneous multiple reads/writes from/to the on-chip memory. However, current FPGAs only comprise dual-port on-chip memories, which hinder simultaneous multiple read/write (R/W) operations needed for parallel computing. Although several multi-ported memories are proposed in the literature, these designs become complex due to the extra logic and routing used for techniques/architectures to provide an arbitrary number of R/W ports for simultaneous multiple R/W operations. Furthermore, most of the existing multi-ported memories only provide an arbitrary number of uni-directional R/W ports. There is only one existing multi-ported memory design in the literature that provides bi-directional R/W ports. Unlike uni-directional ones, bi-directional multi-ported memories give more flexibility to the designers, since the number of read and write transactions can be changed as needed on-the-fly at any time. Previously, we introduced unique and efficient uni-directional multi-ported memories, which were created in such a way to significantly reduce the design and routing complexity. In this research work, we introduce novel, unique, and efficient bi-directional multi-ported memory architectures to provide an arbitrary number of bi-directional R/W ports. Our proposed bi-directional multi-ported memories are designed in such a way to dramatically reduce the design and routing complexity by eliminating the circular paths that typically exists in the current multi-ported memories in the literature, while enhancing operating frequency and area-efficiency. To the best of our knowledge, no similar work exists in the literature that provide multi-ported memory designs without the circular paths. Experiments are performed to evaluate the feasibility and efficiency of our bi-directional multi-ported memory designs. These results and analyses illustrate that our bi-directional multi-ported memories are far more efficient compared to the existing ones in the literature. Due to lower design and routing complexity compared to the existing ones, our simplified memories would enable seamless integration to the next-generation FPGAs with minimal design cost.

Variability aware FinFET SRAM cell with improved stability and power for low power applications

PurposeMajor area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits.Design/methodology/approachIn this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power.FindingsThe cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384 mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed.Research limitations/implicationsThe FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used.Practical implicationsSRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array.Social implicationsThe cell can be used for SRAM memory for low power consumptions.Originality/valueThe work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

FinFET SRAM cell with improved stability and power for low power applications.

In this paper, a new 11T SRAM cell using Double gate FET (FinFET technology) has been proposed, cell basic component is the 6T SRAM cell with 4 NMOS access transistors to improve the stability over CMOSFET circuits and also makes it a dual port memory cell. The proposed cell also used a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability which helps in reducing the leakage current, active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at threshold and subthreshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV.At subthreshold operation also, it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Impact of process variation on cell stability also been analyzed.

A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard

For the next-generation video coding standard Versatile Video Coding (VVC), several new contributions have been proposed to improve the coding efficiency, especially in the transformation operations. This paper proposes a unified $32\times 32$ block-based transform architecture for the VVC standard that enables 2D Discrete Sine Transform-VII (DST-VII) and Discrete Cosine Transform-VIII (DCT-VIII) of all sizes. It mainly gives three contributions: 1) The N-Dimensional Reduced Adder Graph (RAG-n) algorithm is adopted to design the minimal adder-oriented computational units. 2) The storage of the asymmetric transform units can be realized in the dual-port SRAM-based transpose memory. 3) The pipelined 2D transformations of mixed block sizes are achieved with the throughput rate of 32 samples per cycle. The synthesis results indicate that this architecture can reduce area by up to 73.1% compared with other state-of-the-art works. Moreover, power saving ranging from 4.9% to 9.9% can be achieved. Regarding the transpose memory, at least 21.9% of the area can be saved by using SRAM.