Dual Material Double Gate Research Articles

Quantum Analytical Model for Inversion Charge and Threshold Voltage of Short-Channel Dual-Material Double-Gate SON MOSFET

Our previous work analytically establishes that silicon-on-nothing (SON) is superior to silicon-on-insulator MOSFET because of its higher immunity to different short-channel effects and increased current driving capability. Moreover, it has also been shown that our analytical model agrees with various simulation results obtained from MEDICI, ATLAS 2-D, and so on. Because of the ultrathin device structure, classical models are not sufficient to determine accurately potential profile, threshold voltage, or charge inversion phenomena for dual-material double-gate (DMDG) SON MOSFET. Hence, in this paper, for the first time, carrier quantization arising due to the ultrathin body has been included to develop an analytical model for ultrathin low-dimensional DMDG SON structure. The 2-D Poisson and 1-D Schrodinger equations have been solved under the dual-material front gate to find the overall potential and inversion charge profile. The deviation of the quantum threshold voltage from the classical one has been calculated and added to the classical threshold voltage to get its quantum counterpart. The proposed model has also been validated against the numerical device simulator ATLAS 2-D.

Device Design Engineering for Optimum Analog/RF Performance of Nanoscale DG MOSFETs

Analog/RF performance of double-gate MOSFETs in the sub-20-nm regime is investigated using ATLAS device simulator. It is shown that graded channel dual material double gate (GCDMDG) achieves higher drain current, peak transconductance, and higher values of cutoff frequency at lower drain currents. This novel architecture also provides better intrinsic gain for an amplifier. A new analog/RF figure of merit, gain transconductance frequency product (GTFP) is proposed that includes both the switching speed and intrinsic gain of the device and is very useful for circuit design. The peak GTFP is observed at the higher end of moderate inversion, slightly above threshold. The GCDMDG device outperforms in terms of GTFP and is more favorable for shorter channel length devices.

Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications

Due to their excellent scalability and better immunity to short channel effects, double-gate (DG) MOSFETs are being earnestly assessed for CMOS applications beyond the 70 nm node of the SIA roadmap. However for channel lengths below 100 nm, DG MOSFETs still show considerable threshold voltage roll off and to overcome this effect, different gate or channel engineering techniques can be widely used. In this paper, the analog and RF performance of a single halo double gate MOSFET implemented with dual-material gate (DMG) technology is investigated with 2D device simulator. This novel structure shows better immunity to short-channel effects like DIBL and improved analog and RF performance. Moreover they exhibit better suppression of hot carrier effect and higher carrier transport efficiency than a single halo double gate MOSFET. The suitability of nanoscale single halo double gate MOSFETs with dual-material gate for circuit applications is examined by comparing the performance of a two stage cascode amplifier and a greater improvement is observed for single halo dual-material DG MOSFET compared to that of the single halo counterpart.

A new two-dimensional subthreshold behavior model for the short-channel asymmetrical dual-material double-gate (ADMDG) MOSFET’s

Based on the exact solution of two-dimensional Poisson’s equation, a novel subthreshold behavior model comprising channel potential, subthreshold swing, and threshold voltage for the short-channel asymmetrical dual-material double-gate (ADMDG) MOSFET’s have been developed. The model is verified by its simulation results that agree well with those of the two-dimensional numerical simulator. Besides offering the physical insight into device physics, the model provides the basic designing guidance for the ADMDG MOSFET’s.

Dual-Material Double-Gate SOI n-MOSFET: Gate Misalignment Analysis

The dual-material double-gate (DMDG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is the leading contender for sub-100-nm devices because it utilizes the benefits of both double-gate and dual-material-gate structures. One major issue of concern in the DMDG-MOSFET is the alignment between the top and the bottom gate that critically influences the device performance. In this paper, we have investigated the effects of gate misalignment in the DMDG SOI n-MOSFET. In this regard, analytical modeling and extensive simulations have been carried out to analyze the gate misalignment effects on device performance like surface potential, electric field, threshold voltage, subthreshold slope, drain-induced barrier lowering, drain current, and transconductance. Considering the fact that gate misalignment can occur on any side of the gate, both source- and drain-side misalignments have been discussed. Analytical and simulated results are found to be in good agreement, which authenticate our proposed model for the DMDG structure.

A New Two-Dimensional Analytical Model for Short-Channel Symmetrical Dual-Material Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors

Based on resultant solution of a two-dimensional (2D) Poisson's equation in the silicon region, a new analytical model for short-channel fully depleted, symmetrical dual-material double-gate (SDMDG) metal–oxide–semiconductor field effect transistors (MOSFETs) has been developed. The SDMDG MOSFET exhibits significantly reduced short-channel effects (SCEs) when compared with the symmetrical double-gate (SDG) MOSFET due to the step potential profile at the interface between different gate materials. It is found that the threshold voltage roll-off can be effectively reduced using both the thin Si film and thin gate oxide. A considerable portion of the large workfunction of metal gate 1 (M1) when laterally merged with the small workfunction of metal gate 2 (M2) can efficiently suppress drain-induced barrier lowering (DIBL) and maintain the low threshold voltage degradation. In this work, not only a precise 2D analytical model of the surface potential and threshold voltage is presented, but also the minimum surface potential in M1 of the shorter channel device that brings about subthreshold swing degradation for the SDMDG MOSFET is discussed. The new model is verified to be in good agreement with numerical simulation results over a wide range of device parameters.

Pearson‐IV type doping distribution‐based analytical modeling of dual‐material double‐gate fully‐depleted silicon‐on‐insulator MOSFET

AbstractA new two‐dimensional model for dual material double gate fully depleted SOI MOSFET is presented. An investigation of potential distribution in the silicon film is carried out with Pearson‐IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. The proposed structure is such that the work function of the gate metal (both sides) near the source is higher than the one near the drain. The analytical model so developed shows a step‐function in the potential along the channel, which screens the drain potential variation by the gate near the drain thereby suppressing the short channel effects (SCEs). The results predicted by the model are compared with those obtained by 2‐D device simulator ATLAS to verify the accuracy of the proposed model. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 979–986, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22319

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET—Two-Dimensional Analytical Modeling and Simulation

In this paper, we present the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, i.e., a dual-material double-gate (DMDG) SOI MOSFET, exhibits significantly reduced short-channel effects (SCEs) when compared with the DG SOI MOSFET. SCEs in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage, and drain-induced barrier lowering. A model for the drain current, transconductance, drain conductance, and voltage gain is also discussed. It is seen that SCEs in this structure are suppressed because of the perceivable step in the surface-potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.