Dual-loop Topology Research Articles

Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0---100 pF capacitive load. The design has been taped out in a $$0.18\,\upmu \hbox {m}$$0.18μm CMOS process. The proposed regulator has a low component count, area of $$0.012\, \hbox {mm}^2$$0.012mm2 and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from a 1.0---1.4 V supply. The measured results for a current step load from 250 to 500 $$\upmu \hbox {A}$$μA with a rise and fall time of $$1.5\,\upmu \hbox {s}$$1.5μs are an overshoot of 26 mV and undershoot of 26 mV with a settling time of $$3.5\,\upmu \hbox {s}$$3.5μs when $${C_L}$$CL between 0 and 100 pF. The proposed LDO regulator consumes a quiescent current of only $$10.5\,\upmu \hbox {A}$$10.5μA. The design is suitable for application with a current step edge time of 1 ns while maintaining $$\Delta V_{out}$$ΔVout of 64 mV.

High- $Q$ Optoelectronic Oscillator Based on Active Recirculating Delay Line and Dual-Loop Topology

A high Q-factor optoelectronic oscillator (OEO) based on an active recirculating delay line and a dual-loop topology is proposed and demonstrated experimentally. The implemented OEO provides a very stable oscillation at 5.4 GHz with a sub-Hz 3-dB bandwidth and a $Q$ -factor in excess of $10^{10}$ . A single side-band phase noise of −74 dBc/Hz is measured at 10 kHz offset, while side modes are significantly suppressed for offset values in the range of 100 kHz–1 MHz.

A Startup Robust Feedback Class-C VCO With Constant Amplitude Control in 0.18 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex></formula>m CMOS

A feedback class-C VCO with constant amplitude control is presented in this letter. Its dual-loop topology helps to stabilize amplitude and ensure startup robustness over process, voltage and temperature (PVT) variations. Besides, this VCO facilitates a direct amplitude calibration method to find optimal point for different applications. A prototype VCO is implemented in a 0.18 $\mu$ m CMOS process. Measurement shows the VCO has a 4.55–5.16 GHz frequency tuning range and a phase noise of ${-}123.3$ dBc/Hz at 1 MHz offset from a 5 GHz carrier with a 2.78 mW power consumption. The FOM is ${-}192.8$ dBc/Hz.

Design and Optimization of Microwave Frequency Synthesizer Based on DDS

This paper introduces a new frequency synthesizer scheme –Nested-mixer DDS driving PLL frequency synthesizer. It is a dual loop topology. The AUX PLL uses high comparison frequency. The main PLL comparison frequency is high and changed continuously. It overcomes the shortcoming of long switching time which happens in the traditional DDS+PLL. Taking some optimized measures helps to further improve the synthesizer performance. Oversampling is used to reduce DDS output spurious level. Optimizing the circuit layout and structure, using 6 layers PCB, making control and data signal lines as a separate layer, and sandwiching it between analog ground and digital ground plane, minimize the external noise impact on the frequency synthesizer. Finally, a high performance microwave frequency synthesizer with high resolution has been achieved. It has been applied successfully to a military transmitter and a measuring receiver.