Dual In-line Memory Module Research Articles

Estimating a Parametric Component Lifetime Distribution from a Collection of Superimposed Renewal Processes

ABSTRACTMaintenance data can be used to make inferences about the lifetime distribution of system components. Typically, a fleet contains multiple systems. Within each system, there is a set of nominally identical replaceable components of particular interest (e.g., 2 automobile headlights, 8 dual in-line memory module (DIMM) modules in a computing server, 16 cylinders in a locomotive engine). For each component replacement event, there is system-level information that a component was replaced, but no information on which particular component was replaced. Thus, the observed data are a collection of superpositions of renewal processes (SRP), one for each system in the fleet. This article proposes a procedure for estimating the component lifetime distribution using the aggregated event data from a fleet of systems. We show how to compute the likelihood function for the collection of SRPs and provide suggestions for efficient computations. We compare performance of this incomplete-data maximum likelihood (ML) estimator with the complete-data ML estimator and study the performance of confidence interval methods for estimating quantiles of the lifetime distribution of the component. Supplementary materials for this article are available online.

Main Memory in HPC

An important aspect of High-Performance Computing (HPC) system design is the choice of main memory capacity. This choice becomes increasingly important now that 3D-stacked memories are entering the market. Compared with conventional Dual In-line Memory Modules (DIMMs), 3D memory chiplets provide better performance and energy efficiency but lower memory capacities. Therefore, the adoption of 3D-stacked memories in the HPC domain depends on whether we can find use cases that require much less memory than is available now. This study analyzes the memory capacity requirements of important HPC benchmarks and applications. We find that the High-Performance Conjugate Gradients (HPCG) benchmark could be an important success story for 3D-stacked memories in HPC, but High-Performance Linpack (HPL) is likely to be constrained by 3D memory capacity. The study also emphasizes that the analysis of memory footprints of production HPC applications is complex and that it requires an understanding of application scalability and target category, i.e., whether the users target capability or capacity computing. The results show that most of the HPC applications under study have per-core memory footprints in the range of hundreds of megabytes, but we also detect applications and use cases that require gigabytes per core. Overall, the study identifies the HPC applications and use cases with memory footprints that could be provided by 3D-stacked memory chiplets, making a first step toward adoption of this novel technology in the HPC domain.

Characterization of 300-GHz Wireless Channel on a Computer Motherboard

This paper presents characterization of 300-GHz wireless channel on a computer motherboard, where several different measurement scenarios have been considered. Results indicate that the presence of the ground plane and/or vertical parallel-plate structures in the channel introduces multipath that, if constructively superimposed, may create a path loss lower than free-space propagation path loss. In addition, it has been found that a few centimeters of vertical misalignment between the transmitter and the receiver result in a path loss greater than 5 dB. Furthermore, the results indicate that vertical components such as dual in-line memory modules with reflection coefficient close to one for all incident angles can be used to create directed non-line-of-sight (LoS) links with wide coherence bandwidth. Finally, for LoS propagation obstructed by large objects, such as a heatsink, the path-loss exponent of 1.77 is found, while the rotating fan causes periodic fading in the received power, indicating that channel equalization techniques will be needed to overcome deep fades. All these results indicate that optimal communications can be achieved by carefully positioning the antennas with respect to the motherboard layout.

Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

ABSTRACTWith the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth–distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.

A study of partitioned DIMM tree management for multimedia server systems

In-memory computing systems have been attracting considerable attention as a method for servicing high-quality multimedia contents. In-memory computing was intended to store entire data sets in the main memory of a computer to eliminate the need to access slow mechanical hard discs and increase the ability to process complex and large volumes of data. Prior studies have proposed a dual inline memory module (DIMM) tree architecture (DTA) as a new structure for implementing the in-memory computing system. The DTA can apply a partitioned DIMM tree policy to efficiently manage memory. However, the partitioned DIMM tree has several drawbacks, including hardware overhead resulting from additional fields in both the translation lookaside buffer (TLB) and the page table and the demand for an additional fast partition area for the fast partition page table (FPPT). To overcome these drawbacks, this paper proposes an advanced TLB management policy for the partitioned DIMM tree, DIMM tree TLB and two new partitioned DIMM tree management policies, fast-FPPT and slow-FPPT. We model the proposed policies using C language and verify them by special workloads in experiments employing a large-capacity memory system. The experimental results show how the proposed policies influence system performance and confirm that they overcome problems in the existing DTA. The simulations revealed a similarity between the performance of systems using the proposed policies and that of the existing DTA model. However, as the proposed policies demand a considerably lower hardware cost than the existing DTA model, the proposed policies are more practical.

Retention-Aware DRAM Assembly and Repair for Future FGR Memories

Refresh operations consume substantial energy and bandwidth in high-density dynamic random-access memory (DRAM) memory. The trend of increasing refresh overhead limits the scalability of DRAM memory that refreshes all cells at the same rate, because the refresh rate setting depends on the worst-case weak cell manufactured in unstable process technology. To cope with this issue, fine-grained refresh (FGR) is proposed to eliminate the unnecessary refresh operations caused by minor weak cells. Even JEDEC's DDR4 DRAM specification announces the support of FGR, which is likely to evolve and become a standard in future DRAM. Unfortunately, according to our key observation, the effectiveness of FGR is greatly confined by the procedure of refresh-oblivious device integration because all memory devices within a module have to be controlled and refreshed in a lockstep way after the step of assembly. In this paper, we are the first to propose a holistic FGR-oriented DRAM optimization framework, retention-aware DRAM assembly and repair (RADAR), to enhance the effectiveness of FGR in DRAM modules. RADAR includes two novel techniques applicable at the stage of DRAM assembly. The first one is retention-aware device clustering that integrates the “compatible” devices to achieve low refresh rate through a preassembly testing and retention-aware matching method. The second technique, Microfix, exploits the hierarchical DRAM array structure and its redundancy to fix critical weak DRAM rows through fine-grained row and subarray remapping. With this optimization architecture, RADAR, the refresh overhead of DRAM dual in-line memory modules can be dramatically reduced as implied in the experiments.

Flex-DIMM – A New High Density Module Form Factor

The Dual In-Line Memory Module (DIMM) has remained relatively unchanged for the past two decades, with exception of an increase in PCB size, I/O pads and layer count. A new generation called Flex-DIMM is introduced by replacing the rigid-PCB substrate with a thin, bifurcated, flexible circuit that enables several improvements; including a thinner cross-section, better signal integrity with lower layer count, better thermal dissipation and ability to be directly mated to the surface of a motherboard. Originally intended for RDIMM applications, the new module may be an ideal solution for clustered microservers.

COP

Protecting main memories from soft errors typically requires special dual-inline memory modules (DIMMs) which incorporate at least one extra chip per rank to store error-correcting codes (ECC). This increases the cost of the DIMM as well as its power consumption. To avoid these costs, some proposals have suggested protecting non-ECC DIMMs by allocating a portion of memory space to store ECC metadata. However, such proposals can significantly shrink the available memory space while degrading performance due to extra memory accesses. In this work, we propose a technique called COP which uses block-level compression to make room for ECC check bits in DRAM. Because a compressed block with check bits is the same size as an uncompressed block, no extra memory accesses are required and the memory space is not reduced. Unlike other approaches that require explicit compression-tracking metadata, COP employs a novel mechanism that relies on ECC to detect compressed data. Our results show that COP can reduce the DRAM soft error rate by 93% with no storage overhead and negligible impact on performance. We also propose a technique using COP to protect both compressible and incompressible data with minimal storage and performance overheads.

DECO: DIMM controller efficient for ECC operations

An error-correcting code (ECC) immune to bit errors can make memory performance severely degraded since incomplete-word ECC write requests lead to inefficient operations on a dual in-line memory module (DIMM). A DIMM controller efficient for such ECC operations is proposed. The key idea is that read-to-write and write-to-read operations caused by incomplete-word ECC write requests are split into independent read and write operations, and then the read and write operations are individually scheduled under data coherence constraints. Experimental results show that the proposed DIMM controller achieves 11% shorter memory latency, and 9.3% higher memory utilisation, on average, than the latest conventional DIMM controller in industrial multimedia applications. Moreover, it achieves up to 2.1 times higher memory performance on synthetic benchmarks.

A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems

The emergence of cloud computing has driven the demand for high-density, low-latency and high-speed memory interfaces. For such applications the use of multiple dual-inline memory modules (DIMMs) with multiple ranks enables time-efficient processing of high-volume data. However, the deterioration of the channel frequency response due to the presence of DIMM connectors and multiple ranks makes it challenging to perform low-power read and write (R/W) operations at high-speed. Recent works have demonstrated the use of near-ground signaling (NGS) for low-power operation and signal-integrity enhancement with the aid of transmit supply regulation. In contrast to their differential nature, this paper introduces a single-ended NGS transceiver that achieves 6.4Gb/s R/W operations with the aid of low-power equalization and in-situ reference-voltage calibration over a 3.5 total FR4 PCB routing with more than 25mm of package traces in a dual-rank DIMM memory interface system.

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

The demand for capacity and off-chip bandwidth to dynamic random-access memory (DRAM) will continue to grow as we integrate more cores onto a die. However, as the data rate of DRAM has increased, the number of dual in-line memory modules (DIMMs) supported on a multi-drop bus has decreased. Therefore, traditional memory systems are not sufficient to meet both these demands. We propose the DIMM tree architecture for better scalability by connecting the DIMMs as a tree. The DIMM tree architecture is able to grow the number of DIMMs exponentially with each level of latency in the tree. We also propose application of multiband radio-frequency interconnect (MRF-I) to the DIMM tree architecture for even greater scalability and higher throughput. The DIMM tree architecture without MRF-I was able to scale up to 64 DIMMs with only an 8% degradation in throughput over an ideal system. The DIMM tree architecture with MRF-I was able to increase throughput by 68% (up to 200%) on a 64-DIMM system over a 4-DIMM system. Finally, we propose the partitioned DIMM tree, which allows the scaling of a main memory system to a many-DIMM memory system while still maintaining high throughput. The partitioned DIMM tree is able to improve throughput by an average of 19% up to 35% over the DIMM tree with 256 DIMMs on a single channel.

Power Variability in Contemporary DRAMs

Technology scaling has led to significant variability in chip performance and power consumption. In this work, we measured and analyzed the power variability in dynamic random access memories (DRAMs). We tested 22 double date rate third generation (DDR3) dual inline memory modules (DIMMs), and found that power usage in DRAMs depends on both operation type (write, read, and idle) as well as data, with write operations consuming more than reads, and 1s in the data generally costing more power than 0s. Temperature had little effect (1-3%) across the C to 50 C range. Variations were up to 12.29% and 16.40% for idle power within a single model and for different models from the same vendor, respectively. In the scope of all tested 1 gigabyte (GB) modules, deviations were up to 21.84% in write power. Our ongoing work addresses memory management methods to leverage such power variations.

XTRONIC®: Enabler of Improved Performance with Reduced Precious Metal Usage in Microelectronics

XTRONIC®, a tailored nanocrystalline nickel alloy, has been qualified as a new metal barrier layer replacing pure nickel in many traditional hard and soft gold applications. XTRONIC is produced using a proprietary combination of electroplating chemistry and pulse-reverse applied current waveforms that enables dynamic control of the deposited material's composition and grain structure. The resulting deposits have been shown to provide superior performance in a variety of areas that are critical to microelectronics. These improved performance metrics include resistance to corrosive environments, wear durability, wire bonding, and temperature aging performance. The novel suites of properties possible provide enhanced performance for microelectronics, and can also enable equivalent or improved overall performance even with significant reductions of precious metal use in many applications. Proven areas of application include high-speed backplane connectors and multiple printed circuit board applications such as dual in-line memory module (DIMM) and flash memory card (FMC) applications. In the current paper we focus on properties for printed circuit board applications.

Server-class DDR3 SDRAM memory buffer chip

IBM System i®, System p®, and System z® servers require an efficient ultrareliable high-performance memory subsystem. The fourth-generation IBM advanced memory buffer (AMB) chip provides industry-leading performance, scalability, and reliability for the double-data-rate 3 (DDR3) synchronous dynamic random access memory (SDRAM) subsystems employed across a wide range of server platforms. The new IBM AMB employs a cyclic redundancy code-protected packet-protocol-based 6.4-Gb/s host channel, as well as dual 9-byte/10-byte wide 800 to 1,333-Mb/s SDRAM interfaces with dynamic calibration for optimal signal integrity under varied device and system environmental conditions. Applications support industry-standard dual inline memory module (DIMM) and low-latency high-capacity proprietary DIMM packages in conventional multichannel and redundant array of independent memory system architectures. A fully configured daisy-chain topology contains up to 256 GB of memory per host channel. This paper describes the IBM AMB chip architecture, design, and key engineering aspects.

DRAM errors in the wild

Errors in dynamic random access memory (DRAM) are a common form of hardware failure in modern compute clusters. Failures are costly both in terms of hardware replacement costs and service disruption. While a large body of work exists on DRAM in laboratory conditions, little has been reported on real DRAM failures in large production clusters. In this paper, we analyze measurements of memory errors in a large fleet of commodity servers over a period of 2.5 years. The collected data covers multiple vendors, DRAM capacities and technologies, and comprises many millions of dual in-line memory module (DIMM) days. The goal of this paper is to answer questions such as the following: How common are memory errors in practice? What are their statistical properties? How are they affected by external factors, such as temperature and utilization, and by chip-specific factors, such as chip density, memory technology, and DIMM age? We find that DRAM error behavior in the field differs in many key aspects from commonly held assumptions. For example, we observe DRAM error rates that are orders of magnitude higher than previously reported, with 25,000--70,000 errors per billion device hours per Mb and more than 8% of DIMMs affected by errors per year. We provide strong evidence that memory errors are dominated by hard errors, rather than soft errors, which previous work suspects to be the dominant error mode. We find that temperature, known to strongly impact DIMM error rates in lab conditions, has a surprisingly small effect on error behavior in the field, when taking all other factors into account. Finally, unlike commonly feared, we do not observe any indication that newer generations of DIMMs have worse error behavior.

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

A 1-Gbit DRAM with 5.8-Gb/s/pin unidirectional differential I/Os was implemented by 70 nm DRAM process and a main memory module with dual in-line memory module was assembled. The implemented DRAM chips have control methods for core noise injection and a cyclic redundancy check (CRC) generator for outer-data inner-command architecture. Measurements for bit error rate and jitter performance of the transmitter was performed on an electrical test board which emulates the real memory system's environment. Also, the effect on power noise was analyzed from the DRAM chips with three class values of power decoupling capacitance for the peripheral part. The results show that no additional coding for the differential I/O protection in DRAM, like CRC, is required up to 5.8-Gb/s/pin operation.

Reduction of Transient Far-End Crosstalk Voltage and Jitter in DIMM Connectors for DRAM Interface

The transient far-end crosstalk voltage and the crosstalk-induced jitter of dual in-line memory module (DIMM) connectors are reduced by about 80% by increasing the mutual capacitance between DIMM connector pins with the additional interdigitated-comb-shaped metal-stub patterns on the motherboard. It was confirmed by the far-end crosstalk voltage waveform measurements using TDR and the eye diagram measurements at the data rates of 15 Mbps, 100 Mbps, and 3 Gbps. This reduction technique can be applied to the connectors where the inductive coupling ratio is larger than the capacitive coupling ratio.

Quality improvement by using grey prediction tool compensation model for uncoated and TiAlCN-coated tungsten carbide tools in depanel process of memory modules

Small outline dual in-line memory modules (SO-DIMM) are the memory modules used in notebook computers. This study investigates the SO-DIMM accuracy and tool life using an uncoated and TiAlCN-coated tungsten carbide tool in the depanel process. During the cutting process, the tool operating time of a TiAlCN-coated tool can be extended and the surface quality of SO-DIMM at the cutting edge is better than uncoated tools based on EDS (energy dispersive spectrometer) observation. In the milling process, tool wear is a serious problem for new tools and to solve the problem of dimension variation, this study proposes the use of grey prediction tool compensation to offset the variation and enhance the quality of SO-DIMM. According to the process capability indices within the experimental scope, the quality of memory modules using uncoated and TiAlCN-coated tools using grey prediction tool compensation were shown to improve both its Ca and Cpk values. Thus, the grey prediction tool compensation method has really proven to be workable and can improve the quality of SO-DIMM.

Variable-length segmental transmission line and its design guidelines

Waveform distortion is a serious problem in higher-frequency signals on printed circuit boards (PCBs). To overcome this problem, we have already proposed the segmental transmission line (STL) method, which divides transmission lines into several segments with different line widths. Each line width is adjusted to make the reflection noises cancel each other out in order to minimize the signal distortion. In this research, we first analyze the waveform reshaping mechanism of STL. Next, we apply STL to a dual in-line memory module (DIMM) clock-line for high-speed computers. The results give helpful guidelines for STL designs, which shows the efficiency of STL.

Thermal dissipation of DIMM in Tower-BTX configuration

Natural convection for Dual In-Line Memory Module (DIMM) systems, disposed as predicted by the recent Balanced Technology Extended (BTX) form factor in tower configuration, is numerically studied in this article. The considered physical system is modelled by horizontal air-filled layers bounded by parallel walls in which multiple heat sources are arranged. Three-dimensional simulations are carried-out by using a multi-physical FEM software. The results, obtained for imposed ambient temperature and operative conditions (power supplied to memories), show as thermoconvective instabilities may be produced and consequently complex fluid motion field could be detected. Simulated temperature fields show good agreement with thermal design data proposed by DIMM leading constructors. In order to improve computational performance of the numerical model, a simplified geometry is also proposed and tested for solving the physical problem. The present study contributes in investigation on critical cooling conditions for BTX form factor and in innovative projects of fan-less computer architecture.