Dual-gate High Electron Mobility Transistors Research Articles

A Broadband Voltage Variable Attenuator With High-Power Tolerance and Compact Size Based on Dual-Gate GaN HEMTs

To achieve broadband and high-power tolerance voltage variable attenuator (VVA), this paper replaces the single-gate High Electron Mobility Transistor (HEMT) with a dual-gate HEMT based on the distributed stacked structure VVA proposed by Qorvo, which can effectively reduce the chip area and cost while ensuring the bandwidth and power tolerance. To verify the effectiveness of this method, a DC-30GHz single-gate HEMT structure VVA and a DC-30GHz dual-gate HEMT structure VVA were designed and implemented based on the 0.25μm GaN process, respectively. The experimental results show that compared with the single-gate HEMT VVA, the 0.1dB power compression point ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IP-0.1dB</i> ) of the dual-gate HEMT VVA increases by more than 8 dB, and the insertion loss decreases by 0.9dB, the dynamic range increases by 4dB, and the chip area is reduced by 27%. To the best of our knowledge, this is the first report of a VVA based on a dual-gate HEMT structure, which suggests that a multi-gate HEMT device is certainly a better choice for achieving a broadband VVA or switch with high power tolerance with limited chip area and cost.

Investigation of trapping/de-trapping dynamics of surface states in AlGaN/GaN high-electron mobility transistors based on dual-gate structures

The mechanism of current collapse in AlGaN/GaN high-electron-mobility transistors (HEMTs) passivated with low-pressure chemical vapor deposited (LPCVD)-SiNx layers, is revealed by a double-sweep current-voltage measurement of a dual-gate HEMT structure. It provides an in-situ observation of the trapping/de-trapping process of surface states in HEMTs under high-voltage switching stress, by examining the gate-to-gate surface-hopping leakage IS along with several critical features, such as sweeping-rate and voltage-dependent onset voltage, turn-on slope, onset voltage hysteresis, and current tailing, etc. It is also verified that the plasma-enhanced atomic layer deposited (PEALD) 3-nm -SiNx interfacial layer inserted between the LPCVD-SiNx passivation and the AlGaN barrier, is beneficial for suppressing the surface-trap-induced current collapse in AlGaN/GaN HEMTs.

Improved breakdown characteristic of AlGaN/GaN HEMTs with a width gradient recessed dual-gate structure

A dual-gate (DG) structure utilizing an integrated width gradient DC gate to balance the high-voltage and output current drop was performed for the fabrication of AlGaN/GaN high-electron-mobility transistor (HEMT). In comparison to the traditional single-gate devices, the DG HEMTs combine significantly allowable breakdown voltage behaviour with low gate leakage current and a positive shift threshold voltage, delivering one order of magnitude reduction in leakage current and a 36% improvement in maximum drain bias. The evaluated S parameters substantially exhibit a high power gain potential for DG devices due to the presence of DC gate.

Study of Current Collapse Behaviors of Dual-Gate AlGaN/GaN HEMTs on Si

Surface traps on GaN-based HEMTs (high-electron-mobility transistors) usually result in the increase of channel on-resistance. It becomes worsen when short pulses are applied during high-frequency and high voltage switching. Here we present a dual-gate transistor structure to suppress the dynamic on-resistance increase. The auxiliary gate under a proper fixed voltage is able to induce additional electrons to compensate the channel carrier loss during main gate switching, leading to a lower dynamic on-resistance. In this work, we benchmarked the fundamental electrical properties of both single-gate and dual-gate HEMTs. We further extracted the dynamic electrical properties by stressing the devices with short pulses. The results suggest a significant mitigation of current collapse of a dual-gate HEMT under a proper bias applied on the auxiliary gate electrode. The physical mechanism based on the charge distribution in the channel is employed to explain the observations.

Complete parasitic‐capacitance‐shell extraction of high‐frequency switch‐HEMT equivalent‐circuit model

This paper presents a new solution to a particular problem of high electron-mobility transistor (HEMT) equivalent-circuit modeling, that is, complete parasitic-capacitance-shell extraction of high-frequency single-gate and dual-gate switch-based HEMTs, which is very important to the accuracy of high-frequency HEMT switch models, but not important in the conventional common-source HEMT modeling for amplifier-applications. A full-wave electromagnetic (EM) analysis based method is proposed to analytically extract the complete parasitic-capacitance-shell of single-gate and dual-gate switch-based HEMTs. All the 6 parasitic capacitances of the single-gate switch-based HEMT and all the 10 parasitic capacitances of the dual-gate switch-based HEMT are extracted by linear equations. No resistance parameter is needed to calculate the capacitance-to-ground and the interelectrode-capacitance, and for the first time, all the 10 parasitic capacitances of the dual-gate switch-based HEMT are completely considered and analytically extracted. Then, a consistent and systematic modeling procedure of single-gate and dual-gate switch-based HEMT is verified. With the complete parasitic-capacitance-shells extracted, the accurate intrinsic model of the single-gate HEMT can be directly embedded into the parasitic-shell of the dual-gate HEMT. The predicted scattering parameters of the single-gate and dual-gate series switches fit well with the measurements up to 40 GHz, and accurate linear scalability are also found.

Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells Comprising D- and E-Mode HEMTs

This paper presents monolithic integrated InAlN/GaN NAND and NOR logic cells comprising depletion-mode, enhancement-mode and dual-gate enhancement-mode high electron mobility transistors (HEMTs). The designed NAND and NOR logic cells consist of the depletion-mode and enhancement-mode HEMT transistors integrated onto a single die. InAlN/GaN-based NAND and NOR logic cells with good static and dynamic performance are demonstrated for the first time. Calibrated static and dynamic electrophysical models are proposed for 2D device simulations in Sentaurus Device environment. Sentaurus Device mixed-mode setup interconnects the transistors to NAND and NOR logic circuits which allows analysis and characterization of the devices as a complex system. Circuit models of depletion-mode, enhancement-mode and dual-gate HEMTs are designed and calibrated by experimental results and 2D device simulations. The proposed models exhibit highly accurate results.

Nanoscale dual-gate InAlAs/InGaAs HEMT with improved characteristics

ABSTRACT This paper deals with the DC and Radio Frequency (RF) characteristics of InAlAs/InGaAs-based dual-gate high-electron-mobility transistor (DG-HEMT) for a 50 nm gate length. In single-gate HEMT (SG-HEMT), the gate length having less than 100 nm shows poor transconductance (g m ) which reduces the voltage gain (A v ) and maximum oscillation frequency (f max). To overcome this problem, a dual-gate structure is designed keeping the device dimensions unchanged and a numerical model is developed to study the effect of the dual gate. A comparative study of SG-HEMT and DG-HEMT is presented. For a DG-HEMT, a maximum drain current (Ids ) of 310 mA/mm at Vds = 0.1 V, a peak transconductance (g m_max) of 2294 mS/mm, a cut-off frequency (fT ) of 100 GHz and a maximum oscillation frequency (f max) of 270 GHz have been achieved. For reduced gate length, the DG-HEMT performs better due to the presence of dual gate and double heterojunction.

DC Characteristics of AlGaN/GaN HEMTs Using a Dual-Gate Structure.

Multiple techniques such as fluoride-based plasma treatment, a p-GaN or p-AlGaN gate contact, and a recessed gate structure have been employed to modulate the threshold voltage of AlGaN/GaN-based high-electron-mobility transistors (HEMTs). In this study, we present dual-gate AlGaN/GaN HEMTs grown on a Si substrate, which effectively shift the threshold voltage in the positive direction. Experimental data show that the threshold voltage is shifted from -4.2 V in a conventional single-gate HEMT to -2.8 V in dual-gate HEMTs. It is evident that a second gate helps improve the threshold voltage by reducing the two-dimensional electron gas density in the channel. Furthermore, the maximum drain current, maximum transconductance, and breakdown voltage values of a single-gate device are not significantly different from those of a dual-gate device. For the fabricated single- and dual-gate devices, the values of the maximum drain current are 430 mA/mm and 428 mA/mm, respectively, whereas the values of the maximum transconductance are 83 mS/mm and 75 mS/mm, respectively.

A high-gain high-power amplifier MMIC for V-band applications using 100 nm AlGaN/GaN dual-gate HEMTs

In this paper we present the design and realization of a high-power amplifier in grounded coplanar transmission line technology using AlGaN/GaN dual-gate High electron mobility transistors (HEMTs) with a gate-length of 100 nm to achieve a high gain per stage and high output power. A large-signal model was extracted for the dual-gate HEMT based on the state-space approach. For the fabricated dual-stage amplifier a continuous-wave saturatedoutput power of up to 24.8 dBm (0.84 W/mm) was measured at 63 GHz for 20 V drain bias. A small-signal gain of more than 20 dB was achieved between 56 and 65 GHz.

Gain Improvement of Enhancement-Mode AlGaN/GaN High-Electron-Mobility Transistors Using Dual-Gate Architecture

We demonstrate a dual-gate (DG) AlGaN/GaN high-electron-mobility transistor (HEMT) structure with enhancement-mode (E-mode) operation. The DG device consists of an E-mode gate and a depletion-mode (D-mode) gate instead of the dual D-mode gate electrodes used in previously reported works; thus no negative voltage supply is required when the DG device is used in amplifier circuits. The E-mode DG HEMTs exhibit similar DC characteristics to E-mode single-gate devices but show a 9 dB gain improvement at 2.1 GHz under the same bias conditions. The power gain improvement can be attributed to the higher output impedance and lower feedback capacitance in the DG structure.

High-power AlGaN∕GaN dual-gate high electron mobility transistor mixers on SiC substrates

The first demonstration of dual-gate AlGaN/GaN high-electron-mobility transistors (HEMTs) for high-power mixers is presented. The 0.7×300 µm gate device achieved the maximum output power of 19.6 dBm and upconversion gain of 11 dB at 2 GHz and 13 dBm and 5 dB at 5 GHz.

Linearity Study on Enhance/Depletion Dual-Gate High Electron Mobility Transitors using Gain Mapping Method

Power gain linearity was studied using gain mapping method for enhance/depletion (E/D) dual-gate high electron mobility transistors (HEMTs). This method contains next steps; S-parameter and drain current were measured for all drain and gate voltage where interested. Maximum stable gain (MSG), maximum available gain (MAG) and H21 parameters were then calculated for frequency which is interested. These parameters were plotted on drain-current and drain voltage plane. By using this method into dual-gate HEMTs, it was found that threshold voltage of the second gates are essential for gain linearity and have its optimum value.

A novel dual-gate high electron mobility transistor using a split-gate structure

The split-gate concept has been applied to dual-gate high electron mobility structures for room-temperature operation. The gates are configured so that the second gate is in close proximity to the gap defined by the split-gate electrodes. This allows both gates to control the carrier density in the same region of the device, so that it is possible to control the threshold voltage for either gate by altering the bias at which the other gate is held. The effect of changing the gate configuration is demonstrated.