Dual-gate FinFET Research Articles

Enhancing Performance of Dual-Gate FinFET with High-K Gate Dielectric Materials in 5 nm Technology: A Simulation Study

Enhancing Performance of Dual-Gate FinFET with High-K Gate Dielectric Materials in 5 nm Technology: A Simulation Study

Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes

In this paper, we present the fabrication method of asymmetric independent dual-gate FinFETs with different gate stack using sidewall spacer patterning and two-step chemical-mechanical polishing (CMP) processes. The fin width is controlled as a result of sidewall spacer patterning. The two-step CMP processes are conducted to separate two gates and to make different gate stacks for each gate, respectively. The fabricated devices can be used for multiple applications by utilizing independent two gates. First of all, the independent two gates offer the flexible threshold voltage modulation properties by applying the second gate (G2) bias with little subthreshold swing degradation. Second, the device can be utilized as a charge trap flash memory cell by trapping electrons in the charge storage layer. These results provide a possible way to fabricate asymmetric independent dual-gate FinFETs having potential as a multi-functional single device.

32 nm Gate Length FinFET: Impact of Doping

ABSTRACT FinFET, a self–aligned double-gate MOSFET structure has been agreed upon to eliminate the short channel effects. In this thesis, we report the design, fabrication and physical characteristics of n-channel FinFET with physical gate length of 32nm using visual TCAD (steady state analysis). All the measurements were performed at a supply voltage of 1.5V and T ox =5nm. We elucidate the impact of doping concentration on the Performance of n-channel 32nm gate length FinFET at 22nm width. The drain current increases gradually when donor ion concentration in source/drain regions increases to 7e20 cm -3 . Adding opposite type of source/drain impurity or decreasing acceptor ion concentration in channel further improves the performance of FinFET. Keywords FinFETs; CMOS; Drain Induced barrier lowering; Silicon-on-insulator 1. INTRODUCTION SOI (silicon on Insulator) basis multi-gate transistor structure is advisable for miniaturization of transistors and adequate for conquering short channel effects [1]. Fragile structured SOI devices are encouraging for escalating CMOS devices into nano-scale regime. One of them is dual-gate FinFET, includes a steep Si fin restrained by self-aligned double gate [2]. The FinFET technology is enticing because the procedure is accessible to implement with existing processing approaches [3]. The technology consists of developing a slender silicon island (fin) by engraving the silicon film [3]. Some of the essential aspects of FinFET are ultra thin Si fin for elimination of short channel effects, lifted source/drain to cut down parasitic resistance and revamp drive current [2]. FinFETs exploit symmetric gates to achieve tremendous performance, but can be fabricated with asymmetric gates so as to target threshold voltage [4]. FinFETs are drafted to benefit numerous fins to attain larger channel widths [4, 5]. Source/Drain pads bridge the fins in parallel. Increment in number of fins leads to boost the current through the device [4, 5]. For example, a device having five fins has five times higher current than single fin device [4]. The leading asset of the FinFET is the ability to exceptionally lower the short channel effects [2, 3, and 4]. In spite of double gate structure, the FinFET is related to its essence, the conventional MOSFET in layout and fabrication [2]. Three dimensional FINFET design is shown in Fig. 1. FINFET comprises a narrow perpendicular fin placed on the exterior of the wafer. Source and drain are crosswise on both sides of fin. This structure is positioned on SOI substrate.

Analysis and design of low power SRAM cell using independent gate FinFET

Scaling of bulk MOSFET faces great challenges in nanoscale integration technology by producing short channel effect which leads to increased leakage. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect. Dual-gate FinFET can be designed either by shorting gates on either side for better performance or both gates can be controlled independently to reduce the leakage and hence power consumption. A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption. A work is focused on the independent gate FinFET technology as this mode provides less power consumption, less area consumption and low delay as compared to other modes. Leakage current and power consumption in independent gate FinFET is compared with tied gate or shorted gate FinFET SRAM cell. Moreover, delay has been estimated in presented SRAM cells. Further, leakage reduction technique is applied to independent gate FinFET 6T SRAM cell.

3D modeling of dual-gate FinFET

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.