Dual Dielectric Layers Research Articles

A high-performance organic thin-film transistor with Parylene/PMMA bilayer insulation based on P3HT

This work introduces a pioneering approach in the development of organic thin-film transistors (OTFTs),featuring a double-layer dielectric structure that combines poly(para-xylylene)s (Parylene) and poly(methyl methacrylate) (PMMA) to leverage the high insulation properties and high surface polarity of Parylene with the low insulation properties and low surface polarity of PMMA. This combination results in devices that showcase significantly enhanced electrical performance, including superior charge carrier mobility, increased current on/off ratios, and greater transconductance. Utilizing poly(3-hexylthiophene) (P3HT) for the active layer, the study demonstrates the advantage of the dual dielectric layers in minimizing hysteresis in the transfer curve, thereby facilitating the systematic growth of the organic active layer and enhancing electrical conductivity over single-layer alternatives. The superior performance of the Parylene/PMMA double-layer insulating structure opens new avenues for the advancement of organic electronics, presenting methodologies for performance optimization and expanding the application spectrum of OTFTs.

Capacitive Pressure Sensor Combining Dual Dielectric Layers with Integrated Composite Electrode for Wearable Healthcare Monitoring.

Foot activity can reflect numerous physiological abnormalities in the human body, making gait a valuable metric in health monitoring. Research on flexible sensors for gait monitoring has focused on high sensitivity, wide working range, fast response, and low detection limit, but challenges remain in areas such as elasticity, antibacterial activity, user-friendliness, and long-term stability. In this study, we have developed a novel capacitive pressure sensor that offers an ultralow detection limit of 1 Pa, wide detection ranges from 1 Pa to 2 MPa, a high sensitivity of 0.091 kPa-1, a fast response time of 71 ms, and exceptional stability over 6000 cycles. This sensor not only has the ability of accurately discriminating mechanical stimuli but also meets the requirements of elasticity, antibacterial activity, wearable comfort, and long-term stability for gait monitoring. The fabrication method of a dual dielectric layer and integrated composite electrode is simple, cost-effective, stable, and amenable to mass production. Thereinto, the introduction of a dual dielectric layer, based on an optimized electrospinning network and micropillar array, has significantly improved the sensitivity, detection range, elasticity, and antibacterial performance of the sensor. The integrated flexible electrodes are made by template method using composite materials of carbon nanotubes (CNTs), two-dimensional titanium carbide Ti3C2Tx (MXene), and polydimethylsiloxane (PDMS), offering synergistic advantages in terms of conductivity, stability, sensitivity, and practicality. Additionally, we designed a smart insole that integrates the as-prepared sensors with a miniature instrument as a wearable platform for gait monitoring and disease warning. The developed sensor and wearable platform offer a cutting-edge solution for monitoring human activity and detecting diseases in a noninvasive manner, paving the way for future wearable devices and personalized healthcare technologies.

Ka-Band MMIC Using AlGaN/GaN-on-Si With Recessed High- Dual MIS Structure

This letter reports the excellent radio frequency output characteristics of AlGaN/GaN-on-Si power amplifier (PA) monolithic microwave integrated circuits (MMICs) operating at the Ka-band, employing a recessed metal–insulator–semiconductor (MIS) structure with SiN x /HfON dual dielectric layers. The fabricated 0.15- $\mu \text{m}$ AlGaN/GaN-on-Si high electron-mobility transistor (HEMT) exhibited a low OFF-state current and reduced current collapse in comparison with the conventional Schottky gate HEMT; therefore, an enhanced output power of the PA MMIC is achieved. The fabricated two-stage PA MMIC exhibited a continuous-wave output power of >29 dBm with a power-added efficiency (PAE) of 14.5% at the drain voltage of 20 V, at 26.5 GHz.

Organic flash memory on various flexible substrates for foldable and disposable electronics

With the emergence of wearable or disposable electronics, there grows a demand for a flash memory realizable on various flexible substrates. Nevertheless, it has been challenging to develop a flash memory that simultaneously exhibits a significant level of flexibility and performance. This is mainly due to the scarcity of flexible dielectric materials with insulating properties sufficient for a flash memory, which involves dual dielectric layers, respectively, responsible for tunneling and blocking of charges. Here we report ultra-flexible organic flash memories based on polymer dielectrics prepared by initiated chemical vapor deposition. Using their near-ideal dielectric characteristics, we demonstrate flash memories bendable down to a radius of 300 μm that exhibits a relatively long-projected retention with a programming voltage on par with the present industrial standards. The proposed memory technology is then applied to non-conventional substrates, such as papers, to demonstrate its feasibility in a wide range of applications.

The effect of inorganic/organic dual dielectric layers on the morphology and performance of n-channel OFETs.

The optimization of dual dielectric layers by incorporating poly(vinyl alcohol) (PVA), poly(methyl methacrylate) (PMMA), polystyrene (PS) or poly(4-vinylphenol) (PVP) in combination with Al2O3 resulted in immensely improved OFET characteristics with N,N'-bis(cyclohexyl)naphthalene diimide (NDI-CY2) as the active material. The influence of the polymer dielectric layer on the growth morphology of NDI-CY2 and the structural characterization were investigated using atomic force microscopy (AFM) and thin film XRD analysis. The bottom-gate top-contact OFET devices fabricated on glass substrates with Al contact electrodes demonstrated excellent n-channel behavior in the presence of the Al2O3/PVA dual dielectric with the highest electron mobility (μe) value of 0.08 cm(2) V(-1) s(-1), threshold voltage (VTH) as low as 0.5 V and current on/off ratio (ION/IOFF) of 10(4) with an operating voltage of 5 V respectively under vacuum.

Excellent carrier mobility of 0.24 cm2/Vs in regioregular poly(3-hexylthiophene) based field-effect transistor by employing octadecyltrimethoxysilane treated gate insulator

The polymer field-effect transistor based on regioregular poly(3-hexylthiophene) (rr-P3HT) with excellent field-effect mobility up to 0.24 cm2/V s is demonstrated by spin-coating rr-P3HT onto octadecyltrimethoxysilane treated gate insulator followed by thermal annealing of rr-P3HT at 180 °C. This mobility is practically applicable in driving circuits of liquid crystal displays (greater than 0.1 cm2/V s) and close to the highest reported value (0.28 cm2/V s) for rr-P3HT but there a different coating method or dual dielectric layers was used. This impressive mobility can be attributed to the increase in structural ordering of rr-P3HT molecules as supported by x-ray diffraction measurement.

Charge transport and trapping phenomena in off-stoichiometric silicon dioxide films

The electrical characteristics of off-stoichiometric silicon dioxide films have been investigated. The off-stoichiometric oxide films studied had an excess atomic silicon (Si) content in the range of 1%–6%. Raman spectroscopy and photoconductivity measurements indicate that the excess Si is present as amorphous Si islands or small crystallites embedded in silicon dioxide (SiO2) forming a two-phase material. These films differ in structure from previously reported films where dual dielectric layers of stoichiometric SiO2 and Si-rich SiO2 with ≥13% excess atomic Si were used. These dual dielectric films were observed to produce electron injection from contacting electrodes via the Si-rich SiO2 layer into the SiO2 at lower average electric fields. This injection mechanism was believed to be due to localized electric field enhancement near the SiO2–Si-rich SiO2 interface caused by the curvature of the tiny Si islands in the SiO2 matrix. The current versus voltage characteristics of the off-stoichiometric oxide films which will be discussed here were found to be highly nonohmic, showing an increase in conductivity with increasing excess silcion content in the material. At low fields (≲1 MV/cm), these films have a very small conductance with leakage current densities smaller than 10−11 A/cm2 at room temperature. Furthermore, the effect of permanent charge trapping was observed to decrease in these films with increasing Si content. It is proposed that the electron transport across the film is controlled primarily by tunneling between the silicon islands with a reversible space charge region ≲150 Å in extent near the injecting contact, limiting the current measured in the external circuit. It is also proposed that the decrease in permanent electron trapping is associated with this conduction mechanism and/or the possibility of trapped electrons in the SiO2 phase tunneling to the Si islands. With the incorporation of these off-stoichiometric oxides into electrically-alterable read-only-memory devices, extended write/erase cycling (by at least four orders of magnitude) beyond that normally observed for equivalent devices using stoichiometric SiO2 layers is demonstrated due to the reduction in permanent electron trapping in the oxide layer and its effect on the electric fields.

Processing and Properties of Cw Laser-Recrystallized Silicon Films on Amorphous Substrates

ABSTRACTCW laser recrystallization has been used to process silicon thin films as an integral step in semiconductor device fabrication. On continuous films of polycrystalline silicon, a silicon-nitride encapsulant is used to control surface morphology during laser recrystallization. For thin films on bulk glass substrates it is necessary to pattern the silicon layer in order to minimize microcracking as well as to control recrystallization. Over single crystal silicon substrates, test devices have been fabricated in silicon islands on dual-dielectric layers. Materials and device evaluation included TEM, current-voltage, capacitance-voltage, and EBIC measurements, and the test devices consisted of p-n junction diodes, MOS capacitors, and MOS field-effect transistors.