DSP Microprocessor Research Articles

Research on Computer System Implementation of ISO14443B Protocol Communication Data Acquisition based on FPGA

As a programmable logic device, FPGA can be used as a bridge for logic adaptation and timing matching between chip components. For example, in a data acquisition system, data of ten channels need to be collected at the same time. In this case, ten identical data acquisition modules can be instantiated in the FPGA to connect ten external data sensor chips respectively by taking advantage of the parallelism of FPGA, so as to realize the logical adaptation of chip devices. In certain applications such as audio processing, video processing, digital communications, encryption, decryption, etc., as a result of the FPGA computing can parallelism, and FPGA is algorithm Yu into hardware, namely a logic gate and a register, so its execution efficiency usually than machine code and assembly language of single thread special micro processing, the need to replace DSP parallel supercomputing occasions and microprocessors.

Development of a DSP-based electronic control system for the active spray boom suspension

When sprayer is in field operation, the entire boom needs to maintain an ideal height with the ground or crop canopy, which can maximize the quality of pesticide application and minimize the negative effect of application on the environment. This paper introduces a design of high-performance boom control system for pendulum active suspension. The system consists of a human machine interface (HMI) and a real-time controller based on DSP microprocessor. Three different control modes, roll control mode, wing height control mode and hybrid control mode, have been developed to meet the needs of different operators. Considering the irregularity of field ground and the inconsistency of crop canopy height, a signal processing and data fusion algorithm was designed. The DSP-based control system is assembled on a 28 m boom with the pendulum suspension, and the step response and sinusoidal tracking tests of the active boom control system are carried out by using a six-degree-of-freedom motion platform. Firstly, the influence of different control parameters on the control performance was tested, and then three different control modes of the control system are tested and compared, for a given 0.1 Hz sine/cosine test signal, the accuracy of boom roll control mode was 90.27%, the accuracy of wing height control mode was 93.0%. The step response test of hybrid control system was carried out, the height difference between the left wing and the right wing decreases to less than 10% of the initial disturbance within 2.35 s, while the roll control system needs 5.71 s, the response time was shortened by 58.84%. Field test results show that under the roll control system, the maximum roll angle of the boom was only 0.841°, and the maximum roll angle of the chassis was 4.041°. The results show that the DSP-based control system can effectively control the movement of the boom and meet the requirements of field use, also the effectiveness of signal processing algorithm and control method has also been verified.

Design and Implementation of the CT Analyzer on the Basis of the Low Pressure Test Principle

CT analyzer is a necessary instrument of on-site verification accuracy of current transformer. Traditional current transformer testing methods is mainly the differential method. Because of the limited by the principle, the current transformer of the on-site verification is very inconvenient. The CT analyzer designed and developed in this paper use the new method of indirect test - low pressure method, which gets current transformer contrast and angle difference by measuring the internal parameters of the CT. According to the design method of intelligent instrument, by combining with the digital sampling technology, taking DSP microprocessor as the core, and using the advanced digital signal processing method, use only one instrument current transformer can be realize the field test, which effectively resolve the problems of current transformer field test.

A real-time estimation approach of the electric power harmonics by measuring discrete spectrum energy center of symmetric windows

Purpose Significant amount of harmonics and inter-harmonics are being injected into the power system because of the increasing use of power electronics and large non-liner loads. Therefore, analyzing their contents in real time is necessary. Design/methodology/approach The frequency and phase of an electric power harmonic or inter-harmonic can be estimated by using the discrete spectrum energy center of symmetric windows, the amplitude calculation of an electric power harmonic or inter-harmonic can be calculated by using the Pasival theorem, and their relative estimation error is only decided by the distribution of windows’ energy in the frequency domain, which equals the proportion of the spectrum energy occupied in the side lobe to the whole. Findings The results of the digital simulation and experimental tests show that the method proposed in this paper has the same measurement precision as and more advantages in computational complexity and burden over other methods, which are based on multipoint interpolation or interpolation polynomial windowed. Originality/value The method is very suitable to be used to real-time measurement in a single chip DSP micro-processor.

Design of an Efficient Low Power Multiplier: Combining Reversible and an Ancient Vedic Method Approach

Background: Multiplier is very important block which is being used in number of devices like DSP processor and microprocessors. Power consumption by multipliers decides the battery life of all these devices. Researchers are continuously striving for the multiplier which consumes less power but as the most dominant technology till now is CMOS, their efforts are not giving fruitful results due to physical constraints of CMOS device. Methods: In the proposed design used a reversible computing methodology and for circuit designing of multiplier used a QCA Cells. Findings: By combination of reversible computing and ancient Vedic method, a low power and high speed multiplier is proposed. Improvements: With this proposed technique, the Garbage outputs are reduced by 25%, numbers of gates are reduced by 5.40%, numbers of constant inputs are reduced by 6.89%, Quantum cost is reduced by 7.89% and TRLIC factor of this vedic multiplier is reduced by 16.89%.

Embedded Robot Vision System Based on DSP

Aim at the real-time problem of industrial robot vision system, design a embedded robot vision system based on DSP microprocessor. This system can use CCD camera and the ultrasonic sensor to collect the target environment information. It also can use the processor DSP to process the images and recognize target. And then through the communication module, send results in the form of wireless to the upper computer, providing target object information for robot control layer. This system completes the software and hardware system design, image collection & processing and robot control, as well as meet the real-time requirements of machine vision system.

Power-Aware Alternative Adder Cell Structure Using Swing Restored Complementary Pass Transistor Logic at 45nm Technology

In this paper, a novel low power 20T alternative adder cell featuring modified swing restored complementary pass transistor logic (SR-CPL) is proposed. This alternative adder cell structure performs better in terms of power dissipation, propagation delay and power-delay-product (PDP) when compared with 26T SR-CPL and other adder cells implemented using conventional logic styles. As compared with 26T SRCPL adder cell, the proposed adder cell reduces power by 23.15%, delay by 6.15% and PDP by 27.91%. This design is carried-out using a TSMC 45nm CMOS technology in Cadence Virtuoso Analog Design Environment at 45nm technology and simulated using Spectre simulator. This adder cell can be used as a computation element in various DSP architectures and microprocessors resulting in high performance.

Analysis and comparison of current control methods on bridgeless converter to improve power quality

In this paper, the performance analysis of power factor correction (PFC) current control methods is presented for a bridgeless converter operating under continuous conduction mode (CCM). The bridgeless converter has been proposed using proportional-integral control (PIC), average sliding control (ASC) and predictive current control (PCC) methods to obtain unity power factor (PF) and lower total harmonic distortion (THD) of input current. Several PFC methods have been developed to satisfy the international standards such as IEC 61000-3-2 and IEEE 519-1992. The detailed steady-state theoretical analysis of the bridgeless converter is presented, which is verified by simulations and experiments carried out on 600W and 50kHz. The performance of the current control methods for the bridgeless converter is investigated by a Matlab/Simulink program. The experiments performed in the laboratory under input voltage and load variation ranges verify the theoretical and simulation studies. The control methods are programmed by the TMS320F2812 DSP microprocessor.

A DSP-Based Control System for Precision Variable Rate Fertilization

A real-time control system with TMS320F2812 DSP microprocessor as a control core for precision variable rate fertilization was designed, which were composed of the power system, DSP microprocessor controller, executive mechanism for variable rate fertilization, data storage module, speed test module and human-computer interaction module. A human-computer interaction interface system based on data storage and graphics was developed and the main control program was programmed. When the control system is working, the fertilizer rate is firstly entered by human-computer interaction interface, nextly the fertilizer rate and speed information are read into the DSP controller, and then the speed information is transmitted to monitor, finally the output pulses needed by motors are calculated, so the fertilizer rate can be controlled accurately. An experiment was conducted in the laboratory environment. The results showed that the error of fertilization rate of each fertilizer element was nitrogen (N: 0.05%), phosphorus (P:0.73%) and potassium (K:1.16%) respectly, and the consistency variability coefficient of fertilization rate of each fertilizer was nitrogen (N: 0.31%), phosphorus (P: 0.32%) and potassium (K: 0.15%) respectly. The control system for precision variable rate fertilization has high precision, good reliability and stability.

An accurate calculation method of the power harmonic parameters based on the delay time theorem of Fourier transform

A new accurate calculation method of electric power harmonic parameters was presented. Based on the delay time theorem of Fourier transform, the frequency of the electric power was calculated, and then, suing interpolation in the frequency domain of the windows, the parameters (amplitude and phase) of each harmonic frequency signals were calculated accurately. In the paper, the effect of the delay time and the windows on the electric power harmonic calculation accuracy was analysed. The digital simulation and the physical measurement tests show that the proposed method is effective and has more advantages than other methods which are based on multipoint interpolation especially in calculation time cost; therefore, it is very suitable to be used in the single chip DSP micro-processor.

A new high–speed FPGA and Ethernet Based Embedded Data Acquisition System

Analysis the overall structure and the hardware design of new data acquisition system. This system take FPGA as the main chip, and control multi–channel AD chip to collect data. This work eventually use the Cyclone II family EP2C70F672C8N chip as the main chip to achieve, relative to other design which uses such as DSP and ARM microprocessor, internal control circuit is simple and reliable, and has more power and cost advantages. Data transmission could through switches and routers to achieve the data collection and transmission of any distance, at LAN conditions, the maximum data rate can reach 80Mbps.

A New CW CO2Laser with Precise Output and Minimal Fluctuation by Adopting a High-frequency LCC Resonant Converter

The current study proposes the design of a hybrid series-parallel resonant converter (SPRC) and a three-stage Cockcroft-Walton voltage multiplier for precisely adjusting the power generated by a continuous wave (CW) <TEX>$CO_2$</TEX> laser. The design of a hybrid SPRC, called LCC resonant converter, is described, and the fundamental approximation of a high-voltage and high-frequency (HVHF) transformer with a resonant tank is discussed. The results of the current study show that the voltage drop and ripple of a three-stage Cockcroft-Walton voltage multiplier depend on frequency. The power generated by a CW <TEX>$CO_2$</TEX> laser can be precisely adjusted by a variable-frequency controller using a DSP (TMS320F2812) microprocessor. The proposed LCC converter could be used to obtain a maximum laser output power of 23 W. Moreover, it could precisely adjust the laser output power within 4.3 to 23 W at an operating frequency range of 187.5 to 370 kHz. The maximum efficiency of the <TEX>$CO_2$</TEX> laser system is approximately 16.5%, and the minimum ripple of output voltage is about 1.62%.

Design of Fuzzy PID Controller for Water Level of Boiler Steam Drum Based on DSP

A control system for water level of boiler steam drum based on DSP microprocessor is designed in this paper. The technique of fuzzy control was applied to controlling the water level of the steam drum, the operational principle and application of the fuzzy-PID arithmetic are described. The water level controller with good control effect is developed. Firstly the hardware structure of system is introduced in the paper and then investigates the fuzzy-PID arithmetic carry out, and finally, the simplified program flowchart are given.

A DSP based power factor correction converter to reduce total harmonic distortion of input current for improvement of power quality

This paper proposes a controlled approach to be used in power factor correction (PFC) circuits to decrease total harmonic distortion (THD) of input current by eliminating the input current harmonics. This method removes the problems of the conventional PFC converters. Since in conventional PFC circuits the input current is controlled to follow the ac input voltage, it will have the same harmonics of the input voltage. This is an important disadvantage of the conventional method especially when the input voltage is distorted. In this approach, a sinusoidal signal is generated by the DSP microprocessor and is used as reference in controlling the converter switch to obtain a sinusoidal input current based on zero crossing points of distorted input voltage. Due to the reflection of input voltage distortions to the output voltage, an adaptive digital FIR filter is designed and embedded into the voltage control loop. The feed forward is also used into the control algorithm. The implementation of feed forward and adaptive digital FIR filter improves the converter performance to obtain a near unity power factor correction with lower input current THD. Average current control mode is implemented and operated in continuous conduction mode. The experiments performed in the laboratory for different cases of operation verify the theoretical and simulation studies performed in MATLAB/Simulink. The control approach is programmed by the TMS320F2812 DSP microprocessor. The experimental results are good in accordance with IEC 61000-3-2 Current Harmonic Standard.

A uniform laser energy density controller for the rapid prototype processing

Rapid prototyping has become popular nowadays as the lifecycles of commercial and consumer products have been shortened to quarters or even months. The rapid prototyping technology provides a modern way to examine rapid contour changes on products which have forced designers and manufacturers to make new designs, jigs, tools, and molds in the past. Unlike the traditional machining of material, rapid prototyping utilizes technologies, such as stacking, etching, and laser processing, to produce models of designed articles within time and cost limits. Algorithms to control the processing are required and important to the success of rapid prototyping. This study has focused on laser energy control for the processing of Ceramic Laser Sintering rapid prototyping which will sinter ceramic powders into a solid object. Instead of the open‐loop constant laser energy applied in current laser machining, to improve the quality of the prototyping, a uniform laser energy algorithm and controller is developed and tested. The controller can automatically adjust the laser energy applied according to the distance traveled with position feedback. The developed method has been implemented on an embedded DSP microprocessor and CPLD controller to demonstrate its applicability. The experimental data has shown that consistent laser processing quality can be achieved with proper uniform laser energy control, which implies the feasibility of applying this developed uniform laser energy control algorithm to Ceramic Laser Sintering rapid prototyping processing.

Design of Vector Register Architecture in DSP Processor for Efficient Multimedia Processing

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrixvector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

Functionally Fault-tolerant DSP Microprocessor using Sigma–delta Modulated Signals

The occurrence of soft-faults in digital circuits due to single event upsets (SEU) caused by particle hits has been reported in many works, and it has been claimed that, as the transistor dimensions shrink, multiple and simultaneous faults will be a common scenario in future technologies. Many techniques have been proposed to cope with these kinds of faults, most of them based on hardware or software redundancy. In this work, we present a new paradigm, which is based on signal redundancy, that is, the signal to be processed will contain a certain amount of redundancy, in such a way that, even under the occurrence of multiple faults, the final results will sustain a good resolution for some applications. A DSP microprocessor that uses the technique was prototyped, and some results are presented and compared to typical n-bits binary coded DSP microprocessor architecture, showing the advantages of using the proposed approach.

A Measuring Method of the Single-Phase AC Frequency, Phase, and Reactive Power Based on the Hilbert Filtering

This paper presents a novel measuring method based on the Hilbert filtering for the digital monitoring of the single-phase ac frequency, phase, and reactive power. According to this method, the sampled voltage signal passes a pair of the Hilbert filters. Then, the ac frequency and phase can be obtained by the phase detection and the phase-locked loop algorithm. Additionally, the sampled current signal also makes its phase shift by the other Hilbert filter. The current output is multiplied by the one of the phase-shifted voltage signals, and the reactive power is acquired from the dc component of the product. Because a type of infinite impulse response (IIR) Hilbert filters with low-order and small phase-shift error is adopted, this measuring method cannot only obtain fast and accurate digital monitoring results but also be easily realized with the DSP or other microprocessor programming codes. This method has been successfully applied in the design of a digital multifunctional power instrument

A New On-Line Robust Approach to Design Noise-Immune Speech Recognition Systems

Hereafter, we present a new approach dealing to cope with the harmful effects of noise on speech recognition systems (SRS). This approach is oriented to hardware redundancy and it is essentially a modification of the classic Recovery Blocks scheme. When compared to conventional approaches using Fast Fourier Transform (FFT) and Hamming Code, the primary benefit of such a technique is to improve system performance when operating in real (i.e., noisy) environments. The second advantage is related to the considerably low complexity and reduced area overhead required for implementation. We implemented three full versions of the proposed algorithm: one running of a PC microcomputer, and a second one slightly modified to run on a TMS-320C67 Texas DSP microprocessor module. Both of them were described in the C language. Finally, a last implementation was prototyped on a HW-SW development environment based on the same Texas microprocessor and on the FLEX10K20 FPGA Altera Component.

Compiler-controlled memory

Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a. reasonable level of success. The primary limit on the compiler's ability to improve memory behavior is its imperfect knowledge about the run-time behavior of the program. The compiler cannot completely predict runtime access patterns.There is an exception to this rule. During the register allocation phase, the compiler often must insert substantial amounts of spill code ; that is, instructions that move values from registers to memory and back again. Because the compiler itself inserts these memory instructions, it has more knowledge about them than other memory operations in the program.Spill-code operations are disjoint from the memory manipulations required by the semantics of the program being compiled, and, indeed, the two can interfere in the cache. This paper proposes a hardware solution to the problem of increased spill costs---a small compiler-controlled memory (CCM) to hold spilled values. This small random-access memory can (and should) be placed in a distinct address space from the main memory hierarchy. The compiler can target spill instructions to use the CCM, moving most compiler-inserted memory traffic out of the pathway to main memory and eliminating any impact that those spill instructions would have on the state of the main memory hierarchy. Such memories already exist on some DSP microprocessors. Our techniques can be applied directly on those chips.This paper presents two compiler-based methods to exploit such a memory, along with experimental results showing that speedups from using CCM may be sizable. It shows that using the register allocation's coloring paradigm to assign spilled values to memory can greatly reduce the amount of memory required by a program.