Dry Recess Research Articles

Process dependency on threshold voltage of GaN MOSFET on AlGaN/GaN heterostructure

GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) with recessed gate on AlGaN/GaN heterostructure are reported in which the drain and source ohmic contacts were fabricated on the AlGaN/GaN heterostructure and the electron channel was formed on the GaN buffer layer by removing the AlGaN barrier layer. Negative threshold voltages were commonly observed in all devices. To investigate the reasons of the negative threshold voltages, different oxide thickness, etching gas and bias power of inductively-coupled plasma (ICP) system were utilized in the fabrication process of the GaN MOSFETs. It is found that positive charges of around 1×1012q/cm2 exist near the interface at the just threshold condition in both silane- and tetraethylorthosilicate (TEOS)-based devices. It is also found that the threshold voltages do not obviously change with the different etching gas (SiCl4, BCl3 and two-step etching of SiCl4/Cl2) at the same ICP bias power level (20–25W) and will become deeper when higher bias power is used in the dry recess process which may be related to the much serious ion bombardment damage. Furthermore, X-ray photoelectron spectroscopy (XPS) experiments were done to investigate the surface conditions. It is found that N 1s peaks become lower with higher bias power of the dry etching process. Also, silicon contamination was found and could be removed by HNO3/HF solution. It indicates that the nitrogen vacancies are mainly responsible for the negative threshold voltages rather than the silicon contamination. It demonstrates that optimization of the ICP recess conditions and improvement of the surface condition are still necessary to realize enhancement-mode GaN MOSFETs on AlGaN/GaN heterostructure.

Characterization of GaN MOSFETs on AlGaN/GaN Heterostructure With Variation in Channel Dimensions

GaN MOSFETs were developed on an AlGaN/GaN heterostructure in which the drain and source ohmic contacts were fabricated on the AlGaN/GaN heterostructure, and the electron channel was formed on the GaN buffer layer by removing the AlGaN barrier layer. For devices with different types and sizes, discrepant field-effect mobilities were observed and the origins of the discrepancy were analyzed. One reason causing the discrepancy is the discrepancy of gate dimension between the design and fabrication. In devices with only mesa as the device isolation, the real channel width would be larger than the mesa width because a parallel channel might have formed in the isolation region just outside the device mesa. Boron ion implantation was found to be effective to cutoff the current path in the isolation region. Another reason causing the discrepancy is that the real channel length would be larger than the designed one owing to the lithography and gate dry recess process. To extract the correct mobility and effective channel length of the GaN MOSFET fabricated on AlGaN/GaN heterostructure with variation in the channel dimensions, several methods were proposed and compared basing on ring-type MOSFETs.

GaN MOSFET with Boron Trichloride-Based Dry Recess Process

The dry recessed-gate GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure using boron trichloride (BCl3) as etching gas were fabricated and characterized. Etching with different etching power was conducted. Devices with silicon tetrachloride (SiCl4) etching gas were also prepared for comparison. Field-effect mobility and interface state density were extracted from current-voltage (I-V) characteristics. GaN MOSFETs on AlGaN/GaN heterostructure with BCl3 based dry recess achieved a high maximum electron mobility of 141.5 cm2V−1s−1 and a low interface state density.

Influence of Dry Recess Process on Enhancement-Mode GaN Metal–Oxide–Semiconductor Field-Effect Transistors

To gain a flat recess profile with uniform etching depth, dry recess experiment with different inductively coupled plasma (ICP) etching conditions was done on an AlGaN/GaN heterostructure. Trenching effect at the bottom near the sidewall was observed when positive photoresist was utilized and the ICP power was low. The recess profile was improved by adopting SiO2 as the etching mask and increasing the ICP power. GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with different gate recess conditions were fabricated and characterized. The maximum field-effect mobility of 152.8 cm-2 V-1 s-1 and the minimum interface state density of 1.39×1011 cm-2 eV-1 were obtained from the optimized gate recess condition with ICP power of 100 W, bias power of 20 W and etching mask of SiO2.

Highly selective and low damage atomic layer etching of InP∕InAlAs heterostructures for high electron mobility transistor fabrication

Highly selective, low damage atomic layer etching (ALET) technology was developed for dry gate recess during the fabrication of InGaAs∕InP∕InAlAs high electron mobility transistors lattice matched to InP substrates. Etching characteristics of InP layer on top of InAlAs layer and the surface chemistry of the exposed InAlAs layer were investigated by utilizing angular resolved x-ray photoelectron spectroscopy. Finally, InAlAs Schottky diodes were fabricated by utilizing chlorine-based ALET technology and conventional Ar-based dry recess and their electrical characteristics were compared. By using the ALET, the etch selectivity as high as 70:1 was achieved for InP over InAlAs heterostructures and the stoichiometric modification of InAlAs was observed to be negligible after the recess etch process. Schottky diodes fabricated after the ALET exhibited the lower ideality factor and the higher Schottky barrier height compared to those fabricated with Ar-based plasma etching.

Noise Performance of Pseudomorphic AlGaAs/InGaAs/GaAs High Electron Mobility Transistors with Wide Head T-Shaped Gate Recessed by Electron Cyclotron Resonance Plasma Etching

Passivated 0.15 µm pseudomorphic high electron mobility transistors (PHEMTs) were fabricated by combining a wide head T-shaped gate, formed using a dose split method of electron beam lithography, with a short source-gate separation, using formed an electron cyclotron resonance dry recess etching process. The threshold voltage of the devices showed 50 mV variation across three-inch wafers. The extrinsic transconductance and cutoff frequency of the PHEMT devices were 688 mS/mm and 82.6 GHz, respectively. The lowest minimum noise figure, NFmin, of the PHEMT devices was observed around 80% of the saturation drain current at 30 GHz and Vds = 2 V. The devices exhibited a NFmin as low as 0.99 dB with an associated gain of 9.1 dB at 30 GHz. This noise figure value is the lowest data ever reported for a PHEMT device using a dry recess process.

High-performance X-band MMIC LNAs using dry recessedPHEMTs

The authors report compact and low-DC-power LNAs using dry recessed PHEMTs. Dry recess and optimum circuit design were used to reduce the chip size and DC power consumption while improving uniformity and yield. Two-stage PHEMT LNAs showed a noise figure of 1.45 dB at 10 GHz with a 22 dB gain. The active chip size was 0.9 mm/sup 2/ and DC power consumption was 75 mW.

Uniform InAlAs/InP HFET fabricated using selective dry recess etching

Low-frequency noise measurements are used as a diagnostic tool in order to assess the quality of CH 4/H 2 dry recess etching applied to InAlAs/InP heterojunction field effect transistors (HFETs). Devices recessed with conventional wet chemical etching exhibit higher excess noise when compared with the reactive ion etching (RIE) devices. The experimentally observed relative noise in the drain current S Id/I d 2 biased at low drain voltage versus the effective gate voltage Vg = V gs − V p shows the same behaviour on both devices. We find that the noise can be explained by noise fluctuations in the series resistances R GS and R GD the source and drain side of the channel, respectively, and noise fluctuations in the channel R ch. Dry-etched devices exhibit low series resistances (1.6 Ω mm) compared to wet-etched devices (2.4 Ω mm). The improvement of the noise spectra for the dry-etched devices can be explained by the reduction of the series resistances noise, which is due to the decrease of the series resistances.

Low excess noise of InAlAs/InP HFETs fabricatedusing selective dry recess etching

The low frequency noise (10 Hz-100 kHz) behaviour of InAlAs/InP HFETs fabricated using CH/sub 4//H/sub 2/ selective dry recess etching is reported. Devices from the same epitaxial structure fabricated using wet recess etching are also presented for comparison. The dry etching technique improves the drain noise spectral density. This improvement is attributed to the decrease in the source and drain resistance from 2.4 /spl Omega/ mm for the wet recess, to 1.6 /spl Omega/ mm For the dry recess. The equivalent series resistance fluctuations can explain the noise behaviour in both devices. No significant passivation of traps occurs during the CH/sub 4//H/sub 2/ etching process, as demonstrated by noise measurements on annealed dry etched devices.

Characterization of electrical damage induced by CH4/H2 reactive ion etching of molecular beam epitaxial InAlAs

In this article, we report investigations on the effects of methane/hydrogen (CH4/H2) reactive ion etching (RIE) of InGaAs/InAlAs/InP heterostructure materials for high electron mobility transistors, and especially on the electrical properties of the InAlAs layer after dry recess etching of the InGaAs cap layer. The ion etching induced damages in the barrier layer InAlAs are evaluated by diode current–voltage and capacitance–voltage measurements and deep-level transient spectroscopy (DLTS). The I–V data indicate that RIE lowers the Schottky barrier height (φb) and increases the ideality factor. Using low pressure (10 mTorr) RIE processes, with various self-bias voltages, shows that the use of low ion energy is necessary to get good Schottky contacts. Rapid thermal annealing at 400 °C is shown to induce a limited decrease of the dry etching induced defects. However, full recovery of the electrical properties is not achieved. A significant improvement of the Schottky diode electrical characteristics and DLTS spectra is observed after wet etching a 60 Å thick InAlAs layer before metal deposition, indicating that the main damages are concentrated within a short distance from the surface.

0.15 μm T-gate E-beam lithography using crosslinked P(MMA/MMA) developed in ortho-xylene resulting in high contrast and high plasma stability for dry etched recess gate pseudomorphic MODFETs for MMIC production

0.15 μm T-gate E-beam lithography using crosslinked P(MMA/MMA) developed in ortho-xylene resulting in high contrast and high plasma stability for dry etched recess gate pseudomorphic MODFETs for MMIC production

Highly uniform N-InAlAs/InGaAs HEMT's on a 3-in InP substrate using photochemical selective dry recess etching

Large-area photochemical selective dry etching has been developed for use in InGaAs/InAlAs heterojunction fabrication involving CH/sub 3/Br gas and a low-pressure mercury lamp. The etch rate of the InGaAs layer was 17 nm/min and the etch ratio of InGaAs to InAlAs was around 25 to 1. The dry recess was performed for N-InAlAs/InGaAs HEMT's on a 3-in wafer using photochemical etching. The standard deviation of the threshold voltage across the wafer was 18 mV at a threshold voltage of -0.95 V, and the transconductance of 456 mS/mm was obtained for a 1.1- mu m-long gate within a standard deviation of 14.9 mS/mm. >