Dry Etching System Research Articles

Chlorine-Infused Wide-Band Gap p-CuSCN/n-GaN Heterojunction Ultraviolet-Light Photodetectors.

Copper thiocyanate (CuSCN) is a p-type semiconductor that exhibits hole-transport and wide-band gap (∼3.9 eV) characteristics. However, the conductivity of CuSCN is not sufficiently high, which limits its potential application in optoelectronic devices. Herein, CuSCN thin films were exposed to chlorine using a dry etching system to enhance their electrical properties, yielding a maximum hole concentration of 3 × 1018 cm–3. The p-type CuSCN layer was then deposited onto an n-type gallium nitride (GaN) layer to form a prototypical ultraviolet-based photodetector. X-ray photoelectron spectroscopy further demonstrated the interface electronic structures of the heterojunction, confirming a favorable alignment for holes and electrons transport. The ensuing p-CuSCN/n-GaN heterojunction photodetector exhibited a turn-on voltage of 2.3 V, a responsivity of 1.35 A/W at −1 V, and an external quantum efficiency of 5.14 × 102% under illumination with ultraviolet light (peak wavelength of 330 nm). The work opens a new pathway for making a plethora of hybrid optoelectronic devices of inorganic and organic nature by using p-type CuSCN as the hole injection layer.

Deep Dry Etching of Silicon with Scallop Size Uniformly Larger than 300 nm

High aspect ratio features in silicon have broad applications in micro-electro-mechanical systems, microfluidic control and advanced packaging. This structure is usually fabricated by Bosch process, and the corresponding scallop should be controlled. Obtaining large scallop size seems easier than that of small scallop, however, it is a big challenge to obtain uniform large scallop. Herein, by using dry etching system, we demonstrate a novel high aspect ratio silicon trench with scallop size uniformly larger than 300 nm in both single crystal silicon and polycrystalline silicon. Additionally, the difference between single crystal silicon etching and polycrystalline silicon etching is compared. This work is beneficial to understanding the silicon etching mechanism in Bosch process and has potential applications in microelectronic and microfluidic devices.

Metal Etch in Advanced Immersion Tank with Precision Uniformity Using Agitation and Wafer Rotation

In semiconductor wafer fabrication, etching refers to the process of removing unwanted material from wafer surface through a subtractive process. Metal etching is most commonly used in the patterning of metal films for interconnects by establishing specific connection and conduction paths and can be classified by dry etching, de-plating and dissolution of the layers on various substrates such as silicon, SiO2, Si3N4, GaAs, germanium, and sapphire. Dry etching is used to produce very precise etching of vertical channels or vias forming the device features or lines which make up the conductive path because it is anisotropic or etching in one direction. Dry etching is achieved by using chemical gases and plasma in a process chamber so dry etching tools are very large, complex and expensive to purchase and operate. De-plating is a process of electro-chemically removing metal material from the surface of the wafer to an anode by creating a difference in electrical potential between the surface to be etched/de-plated (typically cathode) and the “target” or anode where the material is to be collected. De-plating in single wafer tools has also replaced immersion processing due to the better uniformity it provides. However, De-plating single wafer tools are also very large and expensive to operate and have low throughput (wafers per hour). Dissolution/Immersion is the used of recirculated chemical baths to perform the etching process. In an immersion bath chemical is used to dissolve the metal layer that is unprotected by the mask. Immersion metal etch process has been on the decline because of its isotropic etching property and poor etch uniformity caused by non-uniform chemical flow around wafers in the tank. For the most of etch processes lateral etching is undesired because it occurs on the walls of the features and makes them thinner or misshapen. As a result, most of critical etching steps are performed by dry etching systems. However, if etch uniformity is precise, immersion etching can be used for less critical features in place of complex dry etching and de-plating.

Surface Dependence of pH Sensor on AlGaN/GaN Heterostructure

Glass electrodes are commonly used for pH measurements. The miniaturization, stability and sensitivity of the pH sensor have been improved by introducing Si ISFETs (ion-sensitive field-effect transistors) [1]. However, Si ISFETs are still limited in practical applications especially in high-temperature operation due to the material limitations of silicon and the sensor structure itself. Gallium nitride (GaN) is a good candidate for developing high-speed, high-sensitive and high-temperature pH sensor because of its wide band-gap, chemical stability, low toxicity, and superior conductivity owing to the high saturation velocity and high sheet carrier concentration of the two-dimensional electron gas (2DEG) layer in a AlGaN/GaN heterostructure [2-4]. In this work, GaN-based pH sensors were developed and the surface dependence was evaluated by using different surface layers on the AlGaN/GaN heterostructure.The AlGaN/GaN heterostructure used in this experiment was grown on a (0001) sapphire substrate, which consists of a buffer layer, followed by an undoped GaN layer and an undoped AlGaN barrier layer with thickness of around 12-24 nm. To evaluate the surface dependence, the AlGaN barrier layers were designed to have different aluminum mole fraction of 22%, 24%, 25%, and 35%, respectively. Furthermore, some samples are with thin cap layers of i-GaN, n-GaN and p-GaN, respectively. To fabricate the pH sensor, first, isolation region with depth of 600 nm was formed by inductively coupled plasma (ICP) dry etching system. Ohmic contact for drain and source was then formed using Ti/Al/Ti/Au (50/200/40/40 nm) multilayer followed by annealing process with temperature of 850°C and period of 1 minute in N2 ambient. After dicing step, the chips were mounted on a Teflon substrate by covering all the conducting area with silicone resin to avoid contact with the measurement solutions. The sensing area is an open-gate structure with length of about 600 µm and width of 200-800 µm.A semiconductor parameter analyzer was used to characterize the current-voltage characteristics of the sensor by applying a drain voltage. A gate bias was applied to the solution via a platinum electrode or a standard Ag/AgCl reference electrode. A reference electrode was also used to monitor the voltage in the liquid. Three kinds of buffer solutions were used for measurement, which were phthalate, phosphate and tetraborate pH standard solution.The sensors showed good pinch-off characteristics in the three solutions for all the samples with different surface. The drain current decreased and the threshold voltage had a positive shift with the pH value increasing. The estimated average pH sensitivities (ΔV/pH) were 47.2, 49.5, and 51.8 mV/pH for the samples with cap layer of p-GaN, i-GaN and n-GaN, respectively. While for the samples with aluminum mole fraction of 22%, 24%, 25%, and 35%, the estimated average pH sensitivities were 52.2, 53.5, 54.1, and 55.2 mV/pH, respectively. It demonstrates that the sensitivity of the AlGaN/GaN pH sensor depends on the aluminum mole fraction and increases with the aluminum mole fraction increasing.[1] P. Bergveld, Sensors & Actuators B 88 (2003).[2] G. Steinhoff, Appl. Phys. Lett. 83, 177 (2003).[3] T. Kokawa et al., J. Vac. Sci. Technol. B 24,1972 (2006).[4] B. S. Kang, et al., Appl. Phys. Lett., 91, 012110 (2007).

Application of ICP Deep Trenches Etching in the Fabrication of FBAR Devices

It is presented a fabrication processing of a two step method in deep silicon etching for MEMS applications using an the UK company Surface Technology Systems plc (STS), inductively-coupled plasma (ICP) etch technique STS ICP deep dry etching system. A brief introduction of schematic process of etching deep trenches on silicon substrate is first given, then with two step method for etching deep trenches. The film bulk acoustic resonator (FBAR) devices have been fabricated using STS ICP deep dry etching system with maximum etch rate of 4.6μ m/min, depth more than 450μm and sidewall roughness no more than 0.14μm. At the end of the second step process, the etch selective ratio of silicon to silicon oxygen is enhanced to ensure the device yield. At the same time, the negative effects such as microloads effects, footing effects, lag effects and micrograss effects are suppressed effectively.

Fabrication of Oxide TFTs with Al[sub 2]O[sub 3]/ZnO Gate Stacks Patterned Using a Dry Etching Method

In this paper, we describe a newly developed dry etching process for the fabrication of ZnO-based oxide thin-film transistors (TFTs). The dry etching behavior of ZnO and Al 2 O 3 thin films was systematically investigated by varying the etching gas mixtures and their mixing ratios in a dry etching system using high-density helicon plasma. We fabricated an oxide TFT using an Al 2 O 3 /ZnO gate stack patterned by dry etching and confirmed good device characteristics, in which the field effect mobility and the ratio of on/off drain currents were about 0.8 cm 2 /(V s) and 10 7 , respectively.

The Metallic Contamination Related Whisker Defect During Deposition and Its Removal

We have investigated the whisker defect generation during SiH4 -based silicon film deposition, which is mostly related to metallic impurities on the surface. The metallic impurities from various dry etching systems are heavily detected during device fabrication. The contamination level on silicon surface is around three orders of magnitude higher than that of allowance level. Furthermore, the copper impurities contaminated on the a-Si surfaces are hardly removed even by the acidic solutions with high oxidation-reduction potential values. The contaminants generated the abnormal film growth which was detected after a-Si film deposition. The defect is more than 500nm in size (denote Whisker defect). They can cause serious CMP scratching on the surface or pattern lifting at post process as well as device yield drop. When the a-Si film was deposited on a-Si film, the amount of defect observed was greater than those of other surfaces.

Basic study of a glass substrate in dry etching system

Electrostatic Chucks (ESCs) in the dry etchers for the TFT-LCD fabrications have been investigated briefly. The behaviors of glass encountering electric fields in the presence of plasma were studied. In some conditions, it has been shown that the electric force and the pressure by He backside cooling acting on the glass might be larger than the gravitational force. With a simple model, the stability condition of glass substrate was obtained.

P-67: Brief Study of an Electric Force on a Glass Substrate in a Dry Etching System

Substrate holding systems are widely used in TFT fabrication. As a basic study of ESC system, we have investigated the electric force on a glass substrate in dry etching system. Brief calculation shows that there might be an upward electric force against the gravitational force. This electric force depends on dry etching system and process conditions.

Can dry-etching systems be designed for low damage ab initio?

Photoluminescence intensity measurements from GaAs/AlGaAs and InGaAs/InAlAs quantum well probe structures have been used to study dry-etch damage inflicted in low power reactive ion etching environments. Selective etching has been employed to accumulate damage in the materials under these relatively low damage conditions. The measured data are consistent with calculations for channeling effects of atomic ion species, using a microscopic ion channeling theory. The results indicate that atomic as opposed to molecular ion channeling may be the main mechanism for deep dry-etch damage in these environments, which suggests that gases can be selected as likely to cause low damage.

Chemical Dry Etching of Platinum Using Cl2/CO Gas Mixture

In this study, we have developed a novel method for Pt etching using a chemical dry etching (CDE) system. A volatile etching product was formed during the reaction of Pt with Cl2 and CO. The etch r...

The formation of very flat silicon sidewalls by dry etching

A dry etching system producing very flat wall profiles in bulk silicon is suggested. Wall angles down to 1 degrees were obtained at accurate aligned structures with well defined dimensions. The surface roughness is nearly the same as that prior to the etch. Pattern transfer was carried out in a conventional RIE system. A resist mask was not used but instead a special prepared bonded mask wafer with holes and diffusion channels for the reactive species from the plasma. After the etch this mask wafer is reusable by separating it from the substrate wafer.

7623. Patterning of silicon wafers using the plasma jet dry etching technique: A M Barklund et al, Vacuum, 41, 1990, 899–901

Abstract A very high rate dry etching system based on the plasma jet principle has recently been presented. With this device it is possible to create high concentrations of reactive species. This is done by passing the active gases through a hollow cathode discharge inside a nozzle. A jet stream of radicals will be formed. Silicon substrates can be etched by placing them in the jet stream. With this new technique it is possible to obtain etch rates in silicon which are two orders of magnitude larger than obtained by standard dry etching techniques. Aluminum and SiO 2 have been investigated as mask materials in order to study the possibility of using the plasma jet for micro-patterning. The influence of different processing parameters on the etched structures has been studied.

Patterning of silicon wafers using the plasma jet dry etching technique

A very high rate dry etching system based on the plasma jet principle has recently been presented. With this device it is possible to create high concentrations of reactive species. This is done by passing the active gases through a hollow cathode discharge inside a nozzle. A jet stream of radicals will be formed. Silicon substrates can be etched by placing them in the jet stream. With this new technique it is possible to obtain etch rates in silicon which are two orders of magnitude larger than obtained by standard dry etching techniques. Aluminum and SiO 2 have been investigated as mask materials in order to study the possibility of using the plasma jet for micro-patterning. The influence of different processing parameters on the etched structures has been studied.

Superhigh-rate plasma jet etching of silicon

A new, very high rate dry etching system based on the plasma jet principle is presented. In this device the active gases are fed into the processing vacuum chamber through a small 0.5 mm i.d. nozzle. By applying radio frequency power (13.56 MHz) a hollow cathode discharge is created inside the nozzle. This discharge will be very intense and effective in dissociating the gas mixture used for reactive etching. A jet stream of radicals will be formed. By placing a silicon substrate in front of this jet stream it is possible to perform very high rate reactive etching of silicon. Etch rates as high as 0.1–0.2 mm/min can be easily obtained. It is demonstrated that the etch rate and the width of the etching crater are sensitive to different processing conditions. The width of the etching crater may be smaller than the diameter of the nozzle exit under certain conditions.

An AlGaAs laser with high-quality dry etched mirrors fabricated using an ultrahigh vacuum in situ dry etching and deposition processing system

Highly reliable AlGaAs lasers with dry etched mirrors have been successfully fabricated with an ultrahigh-vacuum in situ processing system, equipped with reactive ion-beam etching (RIBE) and dielectric film deposition chambers. Etched mirror surfaces are protected against air-exposure contamination and nonvolatile-reaction-products adsorption with in situ Al/sub 2/O/sub 3/ passivation subsequent to the CI/sub 2/ RIBE mirror formation. Ion-bombardment-induced damage is repaired by thermal annealing. The annealing effect is enhanced by a contamination-free interface between the etched mirror surface and Al/sub 2/O/sub 3/ passivation film. The lasers exhibit an increase in catastrophic optical damage (COD) level and long-life operation. Their COD levels are twice as high as that for as-etched lasers and are almost the same as those for conventional cleaved lasers. >

Power loss mechanisms in radio frequency dry etching systems

The relation between the total radio frequency (rf) generator output power and the power that is actually dissipated in the plasma in rf dry etching systems was investigated. Power loss processes are described, their relation with the construction of the etch system is demonstrated, and their influence on the discharge is discussed. A method to estimate the power losses occurring in the etch system is described. For three different dry etching systems it is demonstrated that the stray capacitance of the system plays an important role in the power loss processes. In asymmetrical systems the dc self-bias voltage is shown to be a reliable parameter in determining the actual power dissipated in the plasma.

Dry etching systems: gearing up for larger wafers : Ron Iscoff. Semiconductor int., 47 (October 1985)

Borosilicate, BxSiOz (BSG), and borophosphosilicate, BxPySiOz (BPSG) glasses, for applications as intermetal dielectrics in VLSI technology were deposited by plasma enhanced chemical vapor deposition on silicon substrates. Quantitative infrared spectroscopy (IR), Rutherford backscattering spectroscopy (RBS), nuclear reaction analysis (NRA) and X-ray energy dispersion (EDX) were used to obtain the composition of the films. After annealing at temperatures in the range 200 to 900°C under a nitrogen ambient, the concentration of phosphorus and boron in the deposited films is analyzed. It is found that the phosphorus concentration is independent of the annealing temperature. However, the boron concentration decreases with the annealing temperature in both types of glasses. This effect can be attributed to the influence of the concentration of the P-O bonds in the phosphorus doped films, and also to the morphology and hygroscopicity of the films.

Reactive-Ion Etching

Our ability to develop and build ever smaller microelectronic devices depends strongly on the capability to generate a desired device pattern in an image layer (photoresist) by lithography and then to transfer this pattern into the layers of materials of which the device consists. In the past the pattern transfer was almost exclusively accomplished by wet etching. Chemical dissolution of a film region that had to be removed took place in a suitable solvent. Although the wet etching processes stop precisely at a chemically different underlying layer, they typically have isotropic etch characteristics, which cost the researcher control over critical lateral dimensions. Such a tradeoff is not acceptable in the manufacture of micron- and submicron-scale devices, and wet, solution-based etching techniques were replaced in the late 1970s by dry, directional etching processes using plasmas or ion beams. Figure 1 shows a plasma-based dry etching system at IBM. In dry etching processes, surface atoms are removed via momentum transfer from bombarding, directed ions (physical sputtering), thus achieving a directional etch.

Validity of self-bias voltage measurements on insulating electrodes in radio-frequency dry etching systems

It is demonstrated that the measured value of the self-bias voltage on electrodes with an insulating target plate in a radio-frequency dry etching system is strongly influenced by the configuration of the electrode, and may have no straightforward relation with the actual self-bias voltage between the target surface and ground. The mechanism allowing measurement of the self-bias voltage is identified as plasma-induced surface conduction on the insulating target plate assisted by high electric fields at the target plate edge.