Driver Loop Research Articles

A Critical Analysis and Comparison of the Effect of Source Inductance on 3- and 4-Lead SuperJunction MOSFETs Turn-Off

This paper critically compares the turn-off performance of two package solutions, 3-lead (3L) vs. 4-lead (4L), in SuperJunction MOSFETs. It is commonly assumed that the better performance (lower switching losses) of the 4L MOSFET is obtained thanks to the decoupling of the power and driving loops. On the contrary, in this work, the experimental results, circuit models and Kirchhoff laws show that the turn-off improvement (lower turn-off losses) obtained by adopting the Kelvin source is due to the lower inductance of the driver loop of the 4L MOSFET, instead of the decoupling between the driver and power loops. In detail, an inductor is added to the gate path of the 4L MOSFET to obtain a total inductance in the driver loop equal to the 3L counterpart. The experimental results show that the 4L MOSFET presents the same drain current slew rate under this condition, although the driver and power loops are still decoupled.

A Novel SiC Device Model With Power Stage and Gate Driver Uncoupled

Silicon Carbide (SiC) power transistors have fast switching speed but are more inclined to be affected by parasitics. Miller capacitor ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C_gd</i> ) and common source inductor ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_s_com</i> ) are two major cross coupled parameters across gate driver loop and power loop, which cause overshoots, crosstalk and decreased switching speed. To ensure a reliable and efficient switching, the impacts of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C_gd</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_s_com</i> need to be identified and fully compensated in the gate driver. However, state-of-arts failed to provide a straightforward compensation approach with the coupling effects extracted and un-coupled model accurately represented. In this paper, a novel SiC device model with decoupled equivalent miller capacitance and common-mode inductance extracted for both gate driver loop and power loop is presented following the Miller theorem in micro-electronics. The decoupled equivalent circuit is verified to have decent accuracy in predicting the actual SiC switching transients. Furthermore, this paper proposed an improved resonant gate driver (RGD) design using the proposed decoupling model under the effects of common-mode inductance. The pre-charging current and driving pulse width are adjusted to ensure a full resonance driving transient with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_scom</i> . The experimental results show that impact of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_scom</i> is fully compensated, where SiC's <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di_ds/dt</i> is improved from 1.88A/ns to 2.102A/ns, which is close to the results without <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_scom</i> .

A Detailed Analytical Model of SiC MOSFETs for Bridge-Leg Configuration by Considering Staged Critical Parameters

The high operating voltage and switching speed of silicon carbide (SiC) MOSFETs have significant impacts on parasitic elements. This leads to a limitation in the performance of the devices. Especially in the bridge-leg configuration, the coupling of the parasitic elements, in the upper and lower bridge-legs, produces knock-on effects, which complicates the modeling development to reveal the underlying mechanisms. This paper presents a detailed piecewise linear analytical model for bridge-leg configured SiC MOSFETs, which takes into account their characteristics and all parasitic elements. The novelty of the proposed model lies in the fact that the critical parameters in each stage are distinguished flexibly and emphatically according to their influence weights to the corresponding main variables. Therefore, the complexity of the model which considers all parasitic elements is reduced but the critical impacts on the switching processes are carefully kept. The turn-on and turn-off processes are analyzed stage-by-stage in detail with the derived critical parameters equivalent circuits, and the mechanism underlying how each critical parameter influences the model is revealed individually. Furthermore, based on this model, the impact mechanisms and trends of the switching rate variation, the power loop attenuation oscillation, and the driver loop crosstalk phenomenon for different critical parameters are analyzed emphatically. Double pulse measurements with a 600 V/20A SiC MOSFETs based bridge-leg test circuit are used for the experimental verification of the accuracy of the model and the trends of the critical parameters' impacts.

A Spiral Resonators Passive Array for Inductive Wireless Power Transfer Applications With Low Exposure to Near Electric Field

In this article, we demonstrate the near electric field reduction ability of spiral resonators arrays (SRAs) in resonant inductive wireless power transfer (WPT) applications. In particular, we show that a suitably designed planar SRA, placed in the proximity of the driver loop, can significantly decrease the electric field level at the operative frequency, thus reducing the potentially dangerous radiation (i.e., the specific absorption rate) in the case of human exposure. In addition, due to the thin structure of the SRAs, the system is able to enhance the performance with respect to a conventional simple driver–receiver system for a fixed working distance. A systematic study has been performed through electromagnetic simulations to evaluate the optimum number of array unit cells to eventually achieve a compromise between efficiency enhancement and electric field shielding on a two-coil system, selected as a test case. Finally, the numerical results have been confirmed through measurements conducted on fabricated prototypes of the proposed WPT configurations. The introduced solution can be remarkably useful in all the WPT applications requiring a close interaction with human operators where exposure is a concern, such as automotive applications, biomedical implants, and rechargeable devices.

Influence of Parasitic Inductances on Switching Performance of SiC MOSFET

Compared to the silicon power devices, silicon carbide device has shorter switch time. Hence, as a result of the faster transition of voltage (dv/dt) and current (di/dt) in SiC MOSFET, the influence of parasitic parameters on SiC MOSFET’s switching transient is more serious. This paper gives an experimental study of the influence of parasitic inductance on SiC MOSFET’s switching characteristics. Most significance parameters are the parasitic inductances of gate driver loop and power switching loop. These include the SiC MOSFET package’s parasitic inductance, interconnect inductance and the parasitic inductance of dc link PCB trace. This paper therefore focuses on analysis and comparison of different parasitic parameters under various operation conditions in terms of their effect on overvoltage, overcurrent and switching power loss.

C-Stream

Stream processing is a computational paradigm for on-the-fly processing of live data. This paradigm lends itself to implementations that can provide high throughput and low latency by taking advantage of various forms of parallelism that are naturally captured by the stream processing model of computation, such as pipeline, task, and data parallelism. In this article, we describe the design and implementation of C-Stream , which is an elastic stream processing engine. C-Stream encompasses three unique properties. First, in contrast to the widely adopted event-based interface for developing streaming operators, C-Stream provides an interface wherein each operator has its own driver loop and relies on data availability application programming interfaces (APIs) to decide when to perform its computations. This self-control-based model significantly simplifies the development of operators that require multiport synchronization. Second, C-Stream contains a dynamic scheduler that manages the multithreaded execution of the operators. The scheduler, which is customizable via plug-ins, enables the execution of the operators as co-routines, using any number of threads. The base scheduler implements back-pressure, provides data availability APIs, and manages preemption and termination handling. Last, C-Stream varies the degree of parallelism to resolve bottlenecks by both dynamically changing the number of threads used to execute an application and adjusting the number of replicas of data-parallel operators. We provide an experimental evaluation of C-Stream. The results show that C-Stream is scalable, highly customizable, and can resolve bottlenecks by dynamically adjusting the level of data parallelism used.

A Multiloop Method for Minimization of Parasitic Inductance in GaN-Based High-Frequency DC–DC Converter

Gallium nitride high electron mobility transistors (GaN HEMTs) are promising switching devices in high-efficiency and high-density dc–dc converters due to their fast switching speed and small conduction resistance. However, GaN HEMTs are very sensitive to parasitic inductance because of their high switching speed, low-threshold voltage, and small driving safety margin. Parasitic inductance can cause severe voltage overshoot and ringing, which may result in electromagnetic interference issues, false turn-on, or even device breakdown. This paper aims at reducing the parasitic inductance (including power loop inductance and driver loop inductance) by optimizing the layout. First, a multiloop method is proposed to reduce the parasitic inductance. Optimization of both the conventional single-loop structure and the proposed multiloop structure are presented. Second, three kinds of power loop layouts based on the proposed multiloop structure are realized on PCB substrate and one of them is realized on aluminum nitride (AlN) substrate, which has higher thermal conductivity but less copper layers. The power loop inductance on PCB substrate is reduced to 0.1 nH, which is only 25% of the state-of-art layout. The power loop inductance on AlN substrate is reduced to 0.22 nH. Third, the driver loop layout is optimized and achieves 50% reduction of driver loop inductance compared with the conventional single-layer layout. Finally, integrated modules using the proposed layouts are built to validate the analyses and designs.

Towards Compatible and Interderivable Semantic Specifications for the Scheme Programming Language, Part I: Denotational Semantics, Natural Semantics, and Abstract Machines

We derive two big-step abstract machines, a natural semantics, and the valuation function of a denotational semantics based on the small-step abstract machine for Core Scheme presented by Clinger at PLDI'98. Starting from a functional implementation of this small-step abstract machine, (1) we fuse its transition function with its driver loop, obtaining the functional implementation of a big-step abstract machine; (2) we adjust this big-step abstract machine so that it is in defunctionalized form, obtaining the functional implementation of a second big-step abstract machine; (3) we refunctionalize this adjusted abstract machine, obtaining the functional implementation of a natural semantics in continuation style; and (4) we closure-unconvert this natural semantics, obtaining a compositional continuation-passing evaluation function which we identify as the functional implementation of a denotational semantics in continuation style. We then compare this valuation function with that of Clinger's original denotational semantics of Scheme.

On the Equivalence between Small-Step and Big-Step Abstract Machines: A Simple Application of Lightweight Fusion

We show how Ohori and Sasano's recent lightweight fusion by fixed-point promotion provides a simple way to prove the equivalence of the two standard styles of specification of abstract machines: (1) in small-step form, as a state-transition function together with a `driver loop,' i.e., a function implementing the iteration of this transition function; and (2) in big-step form, as a tail-recursive function that directly maps a given configuration to a final state, if any. The equivalence hinges on our observation that for abstract machines, fusing a small-step specification yields a big-step specification. We illustrate this observation here with a recognizer for Dyck words, the CEK machine, and Krivine's machine with call/cc.&lt;br /&gt; &lt;br /&gt;The need for such a simple proof is motivated by our current work on small-step abstract machines as obtained by refocusing a function implementing a reduction semantics (a syntactic correspondence), and big-step abstract machines as obtained by CPS-transforming and then defunctionalizing a function implementing a big-step semantics (a functional correspondence).

On the equivalence between small-step and big-step abstract machines: a simple application of lightweight fusion

We show how Ohori and Sasano's recent lightweight fusion by fixed-point promotion provides a simple way to prove the equivalence of the two standard styles of specification of abstract machines: (1) in small-step form, as a state-transition function together with a ‘driver loop’, i.e., a function implementing the iteration of this transition function; and (2) in big-step form, as a tail-recursive function that directly maps a given configuration to a final state, if any. The equivalence hinges on our observation that for abstract machines, fusing a small-step specification yields a big-step specification. We illustrate this observation here with a recognizer for Dyck words, the CEK machine, and Krivine's machine with call/cc. The need for such a simple proof is motivated by our current work on small-step abstract machines as obtained by refocusing a function implementing a reduction semantics (a syntactic correspondence), and big-step abstract machines as obtained by CPS-transforming and then defunctionalizing a function implementing a big-step semantics (a functional correspondence).

A Simple Application of Lightweight Fusion to Proving the Equivalence of Abstract Machines

We show how Ohori and Sasano's recent lightweight fusion by fixed-point promotion provides a simple way to prove the equivalence of the two standard styles of specification of abstract machines: (1) as a transition function together with a `driver loop' implementing the iteration of this transition function; and (2) as a function directly iterating upon a configuration until reaching a final state, if ever. The equivalence hinges on the fact that the latter style of specification is a fused version of the former one. The need for such a simple proof is motivated by our recent work on syntactic correspondences between reduction semantics and abstract machines, using refocusing.

Analytical loss model of power MOSFET

An accurate analytical model is proposed in this paper to calculate the power loss of a metal-oxide semiconductor field-effect transistor. The nonlinearity of the capacitors of the devices and the parasitic inductance in the circuit, such as the source inductor shared by the power stage and driver loop, the drain inductor, etc., are considered in the model. In addition, the ringing is always observed in the switching power supply, which is ignored in the traditional loss model. In this paper, the ringing loss is analyzed in a simple way with a clear physical meaning. Based on this model, the circuit power loss could be accurately predicted. Experimental results are provided to verify the model. The simulation results match the experimental results very well, even at 2-MHz switching frequency.