Drift-diffusion Device Simulator Research Articles

Role of stress/strain mapping and random dopant fluctuation in advanced CMOS process technology nodes

In this work, biaxial and uniaxial strain techniques are implemented in the channel for both p- and n-type FinFETs necessary for advanced CMOS applications. Stress/strain mapping in strained-Si (n-type) and strained-SiGe (p-type) channels (in trapezoidal tri-gate FinFET devices) are studied through three-dimensional (3D) numerical simulation, with particular focus on the enhancement of drain current. Following the strain/stress profiles simulated, the piezoresistive changes are implemented in the simulator to describe the strain effects on device operation. Further, we have investigated the impacts of random discrete dopant variability on the characteristics of a 14-nm gate length FinFET transistors (both n and p-type) using a 3D finite element quantum corrected drift-diffusion device simulator. We have also found the fluctuation of critical device parameters such as threshold voltage (VTH), sub-threshold slope (SS), on current (ION), and off state current (IOFF), etc., mainly originated from the randomness of distribution of the dopants.

Minimizing performance degradation induced by interfacial recombination in perovskite solar cells through tailoring of the transport layer electronic properties

The performance of hybrid organic-inorganic metal halide perovskite solar cells is investigated using one-dimensional drift-diffusion device simulations. We study the effects of interfacial defect density, doping concentration, and electronic level positions of the charge transport layer (CTL). Choosing CTLs with a favorable band alignment, rather than passivating CTL-perovskite interfacial defects, is shown to be beneficial for maintaining high power-conversion efficiency, due to reduced minority carrier density arising from a favorable local electric field profile. Insights from this study provide theoretical guidance on practical selection of CTL materials for achieving high-performance perovskite solar cells.

Simulation of Charge Transport and Recombination across Functionalized Si(111) Photoelectrodes

A method is described for modeling charge transfer and recombination across functionalized Si(111) photoelectrodes using a 1D solid state drift-diffusion device simulation - wxAMPS. To demonstrate the approach, the effect of charge transport mechanisms on the photoelectrochemical performance of hydrogen and methyl-terminated Si(111) electrodes was analyzed. When contacted with electrolyte, prior literature proposed three charge transfer mechanisms that can affect the performance of functionalized surfaces: a shift in interfacial dipole, a change in surface recombination, or Fermi level pinning. By modeling all three processes using wxAMPS, a shift in interfacial dipole of −0.35 ± 0.05 eV between hydrogen and methyl-terminated Si(111) was concluded to be the predominant effect in these electrodes. This verifies prior hypotheses while predicting a more accurate value of the shift in interfacial dipole than previous theoretical treatment and experimental interpretations.

Physical insights of body effect and charge degradation in floating-body DRAMs

Floating Body one transistor Dynamic Random Access Memories (FBRAMs) have been widely studied and proposed in the literature as an alternative for conventional one transistor/one capacitor DRAMs. FBRAM performance depends on charge degradation during READ and HOLD operations and on the body effect during READ operation, the first setting the amount of the residual non-equilibrium charge during READ operation, and the second setting the effectiveness of this residual charge to modulate the source-body barrier during READ operation. In this work it is proposed a simple analytical charge-based compact model for the body-effect in FBRAMs which is able to reproduce device performance in terms of READ Sense Margin and current ratio. Physical insights of the body effect and charge degradation mechanisms, with particular emphasis to their bias dependence, are discussed in detail. Conclusions can be useful for the choice and the optimization of the bias in FBRAMs. All the discussion is supported by two-dimensional drift–diffusion device simulation on a template double-gate MOSFET.

Statistical study of the influence of LER and MGG in SOI MOSFET

A 3D drift-diffusion device simulation tool with quantum corrections has been applied to study the off-current, threshold voltage and sub-threshold slope variability induced by the metal gate granularity using a Voronoi approach, and line edge roughness using Fourier synthesis, in a 25 nm Si FinFET. The discretization based on the finite element method allows for an accurate description of the 3D geometry. We have simulated 4000 variations of the device to study the metal gate granularity using four different metal grain sizes. The results for the threshold voltage variability ranged from 8.6 mV, for a 3 nm grain size, to 25.9 mV, for a 10 nm grain size. The effect of the grain size was studied and we found an inverse square root dependence of the variability for the three figures of merit. The mean threshold voltage and sub-threshold slope have monotonous decrease with the decrease in metal grain size suggesting that the device power consumption and switching speed can be improved by reducing the grain size. The corresponding threshold voltage variability can reach up to 8.2 mV when RMS = 3 nm and the correlation length is 50 nm.

Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In0.53Ga0.47As GAA MOSFET

We investigate the impacts of random dopant (RD) and gate workfunction variability on the subthreshold characteristics of a 50-nm-gate-length inversion-mode gate-all-around In0.53Ga0.47As MOSFET using a 3-D finite-element quantum-corrected drift-diffusion device simulator calibrated to experimental data. We have studied threshold voltage, off-current, and subthreshold slope variations. The workfunction variations on the subthreshold characteristics dominate and decrease with the reduction in grain diameter. The simulated grain diameters of 10, 7, and 5 nm exhibit threshold voltage standard deviations of 52, 41, and 27 mV, respectively. These values are larger than those observed in TiN-metal-gate Si FinFETs for a similar gate length. The impact of RD fluctuations is negligible when compared with bulk Si MOSFETs, giving a threshold voltage spread of only 6 mV.

3D ‘atomistic’ simulations of dopant induced variability in nanoscale implant free In0.75Ga0.25As MOSFETs

A detailed simulation study of the impact of quantum effects on random dopant induced fluctuations in a 15nm gate length, implant free In0.75Ga0.25As MOSFET is carried out using parallel 3D finite-element drift-diffusion (DD) device simulations and a mesh with atomistic resolution. The DD device simulations are calibrated against finite element heterostructure ensemble Monte Carlo simulations. Three figures of merit for the off-state have been investigated: threshold voltage, off-current, and sub-threshold slope. Quantum confinement effects are taken into account through the density gradient approximation meticulously calibrating carrier density in the channel against 1D Poisson–Schrödinger solutions. We have shown that the net result of including quantum effects, while considering statistical dopant fluctuations, is a decrease in both threshold voltage fluctuations and threshold voltage shift. These results show the opposite trend generally seen in bulk Si MOSFETs simulated using 3D quantum corrected DD simulations with random discrete dopants in the channel region.

Device Simulation for Evaluating Effects of Inplane Biaxial Mechanical Stress on n-Type Silicon Semiconductor Devices

This paper presents a practical method of drift-diffusion device simulation for evaluating the effects of mechanical stress on n-type silicon semiconductor devices. The device simulation incorporates an electron mobility model for considering the effects of stress. In this paper, we focus on stress effects that are induced by applying inplane biaxial stress to the devices. Therefore, two physical phenomena that are attributed to mechanical stress are modeled in the electron mobility model, i.e., the changes in relative population and the momentum relaxation time (intervalley scattering) of electrons in conduction-band valleys. Stress-induced variations of direct-current characteristics on n-type metal-oxide-semiconductor (MOS) field-effect transistors are evaluated using a device simulation including the proposed electron mobility model. Then, the electron mobility model and the simulation method are verified by comparing with experimental results. It is demonstrated that experimental results can be reasonably estimated using this device simulation method. From discussions regarding the electron mobility model, it is suggested that the comprehensive stress sensitivity of MOS devices is larger than that of lightly doped silicon.

A 3-D Statistical Simulation Study of Mobility Fluctuations in MOSFET Induced by Discrete Trapped Charges in SiO $_2$ Layer

The random telegraph signal in nanoscale devices is critically dependent on the spatial distribution and number of trapped charges in the gate oxide. Also, the drain-current fluctuation ΔI <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$_D$</tex></formula> therein is known to be made up of the fluctuations in carrier number and mobility. In this paper, the local potential variation (LPV) arising from the single charge is incorporated into well-known mobility model and the effect of discrete trapped charges in the oxide layer is statistically investigated, using the in-house 3-D drift-diffusion and density-gradient device simulators. The LPV model covers the conventional distributed trapped charge mobility model but it can also accurately account for the observed fluctuations in I <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$_D$</tex></formula> in terms of carrier number and mobility fluctuations.

Direct Tunnelling Gate Leakage Variability in Nano-CMOS Transistors

A comprehensive simulation methodology for the systematic study of gate leakage variability in realistic nanoscale bulk CMOS transistors, on a statistical scale, is presented for the first time. This is based on the Glasgow “atomistic” 3-D drift-diffusion device simulator with density-gradient quantum corrections, which is capable of modeling various sources of stochastic variability, including random dopant fluctuations (RDFs) and oxide thickness fluctuations (OTFs). The capabilities of the simulator are extended to model direct tunnelling of electrons through the gate dielectric by means of an improved Wentzel-Kramer-Brillouin approximation with one model parameter only. The methodology is applied for the detailed study of the gate leakage variability arising from RDFs and OTFs in a 25-nm square-gate n-channel metal-oxide-semiconductor field-effect transistor with conventional architecture. The origins of gate leakage variability and gate current increase due to RDFs and OTFs individually, and in combination, are analyzed for bias conditions that are relevant to static power dissipation in digital CMOS circuits.

Polymer field-effect transistors based on semiconducting polymer heterojunctions

Top-gate polymer field-effect transistors based on charge accumulation in bilayers of two semiconducting polymers have been realized. Holes were confined at the interface between poly(3-hexyl thiophene) (P3HT) and a series of semiconducting polymers with ionization potential higher than P3HT. In contrast to conventional devices based on semiconductor-dielectric interfaces the current was found to saturate at high gate voltages. The more pronounced the current saturation is, the lower the applied source-drain voltage. Generic drift-diffusion device simulations were performed to explain this behavior in terms of the competing processes of charge transport along and charge transfer across the bilayer interface. Our results indicate that in order to block the charge transfer across the heterojunction the offset between the ionization potential of the two polymers needs to be at least 1.0 eV.

Optimization of linear systems for 3D parallel simulation of semiconductor devices: Application to statistical studies

AbstractThe 3D simulators are nowadays essential in semiconductor device modelling in order to study fluctuation effects when devices are scaled to gate lengths approaching nanometre dimensions. To take into account these effects it is necessary to perform statistical studies, which have a high computational cost. The resolution of the linear systems generated by the discretization of partial differential equations is the most time‐consuming part of the simulation process. In this paper we propose an optimization of the linear system solution procedure based on domain decomposition methods implemented in a 3D parallel drift–diffusion device simulator. We have also carried out an analysis of the parallel performance of the device simulator. Numerical results show superlinear efficiency values up to 62 processors in the solution of the Poisson equation. The results were obtained on a Cluster HP Integrity Superdome. Copyright © 2008 John Wiley &amp; Sons, Ltd.

Development of electronic device simulations for educational purposes

A comprehensive set of semiconductor device simulation tools, written in Java, is being developed for instructional use. These interactive programs can be launched from an electronic textbook or from lecture presentation material. At present these tools demonstrate introductory quantum mechanics, several aspects of semiconductor physics, and both zero-current and drift-diffusion device simulations in one dimension. Development of two-dimensional simulations is in progress.

Impact of intrinsic parameter fluctuations on the performance of HEMTs studied with a 3D parallel drift-diffusion simulator

Intrinsic parameter fluctuations in state-of-the-art high electron mobility transistors (HEMTs) are studied using a 3D parallel drift-diffusion device simulator. Two sources of intrinsic parameter fluctuations have been considered: the random discrete dopants in the δ-doped layer and the variations in the material composition of the channel. The effect of those two sources is investigated in a 120 nm gate length pseudomorphic HEMT with an In 0.2Ga 0.8As channel and in a 50 nm gate length InP HEMT with an In 0.7Ga 0.3As channel. We have found that the random discrete dopants in the δ-doping layer are the major factor introducing the variations in the drive current and the device performance. In the devices studied, the variations in the drive current decrease as a function of the gate voltage. Furthermore, at a fixed gate voltage, the variations decrease with the drain voltage in the 50 nm InP HEMT while in the 120 nm PHEMT the variations increase with the drain voltage.

Statistical study of the effect of interface charge fluctuations in HEMTs using a 3D simulator

The intrinsic parameter fluctuations associated with the discreteness of charge and matter become an important factor when the semiconductor devices are scaled to nanometre dimensions. The interface charge in the recess regions of high electron mobility transistors (HEMTs) has a considerable effect on the overall device performance. We have employed a 3D parallel drift-diffusion device simulator to study the impact of interface charge fluctuations on the I-V characteristics of nanometre HEMTs. For this purpose, two devices have been analysed, a 120 nm gate length pseudomorphic HEMT with an In0.2Ga0.8As channel and a 50 nm gate length InP HEMT with an In0.7Ga0.3As channel.

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.

Statistical study of subthreshold characteristics in polycrystalline silicon thin-film transistors

We investigate the influence of grain size variations on device properties of polycrystalline silicon thin-film transistors (poly-Si TFTs) by drift–diffusion device simulations. Employing our grain boundary model which represents the intrinsic variations of grain size [Jpn. J. Appl. Phys., 42, L634 (2003)], the subthreshold characteristics are simulated for the various configurations of grains in the channel region so that the statistical fluctuation of device characteristics is investigated. It is shown that the variations in subthreshold characteristics are caused mainly by the number of grains included in the channel because the grain boundaries act as highly resistive regions. However, as the channel length shrinks, the grain boundary located close to the drain critically determines the channel resistance of poly-Si TFTs and the device characteristics could differ even if the number of grains included in the channel region is the same.

3D Parallel Simulations of Fluctuation Effects in pHEMTs

The use of 3D simulations is essential in order to study the effects of fluctuations when devices are scaled to deep submicron dimensions. A 3D drift-diffusion device simulator has been developed to effectively simulate pseudomorphic high electron mobility transistors (pHEMTs) on a distributed memory multiprocessor computer. The drift-diffusion equations are discretized using a finite element method on an unstructured tetrahedral mesh. The obtained set of equations is solved in parallel on an arbitrary number of processors using the message-passing interface library. We have applied our simulator to a 120 nm pHEMT based on the Al0.3Ga0.7As/In0.2Ga0.8As interface and carried out a calibration to real experimental data.

The internal electric field distribution in bilayer organic light emitting diodes

Abstract The internal electric field distribution in a bilayer 4,4′-bis[N-(1-napthyl)-N-phenylamino]-biphenyl/tris-(8-hydroxyquinoline) aluminium organic light emitting diode has been investigated experimentally using electroabsorption spectroscopy. The experimental results have been compared to those obtained from a drift–diffusion device simulation, further validating the model and highlighting the potential worth of such modelling. With the aid of the simulation, the electric field distribution can be explained in terms of charge carrier accumulation at the interface between the two organic layers, due to the HOMO and LUMO band offsets, and charge injection into the device, demonstrating the influence of contact materials on device behaviour.

On discrete random dopant modeling in drift-diffusion simulations: physical meaning of `atomistic' dopants

We investigate the physics behind the `atomistic' dopant model widely used in drift-diffusion (DD) simulators for the study of statistical threshold voltage variations in ultra-small MOSFETs. It is found that the conventional dopant model, when extended to the extreme atomistic regime, becomes physically inconsistent with the concepts of electric potential presumed in DD device simulations. The split of the Coulomb potential between the long-range and short-range parts associated with discretized dopants is critical for the device simulations under the atomistic regime. A new dopant model to overcome such problems for 3-dimensional DD simulations is proposed by employing this idea.