Drain Stress Voltage Research Articles

Physical Insights Into Electron Trapping Mechanism in the Carbon-Doped GaN Buffer in AlGaN/GaN HEMTs and Its Impact on Dynamic On-Resistance

In this work, a well-calibrated computational framework is used to probe the physical mechanisms leading to electron trapping in the carbon-doped GaN buffer in AlGaN/GaN HEMTs. Device variants having higher lateral electric field were found to exhibit a drastic increase in dynamic ON resistance beyond a critical drain stress voltage. Computations were done while considering trapping on the device surface, with and without accounting for hot electrons, as well as trapping in the GaN buffer. Detailed analysis established electron injection and trapping in the C-doped GaN buffer to be responsible for the observed dynamic ON resistance behavior. Physical insights are provided into the electron injection and trapping behavior by analyzing field evolution near the field plate edge, field-enhanced trapping, and its impact on the leakage current path within the GaN buffer. Finally, the proposed mechanism of field-enhanced electron trapping is validated by computations with device variants having field-independent trapping process and different buffer trap activation energies.

Novel Surface Passivation Scheme by Using p-Type AlTiO to Mitigate Dynamic ON Resistance Behavior in AlGaN/GaN HEMTs—Part II

The underlying mechanism responsible for the unique dynamic ON-resistance behavior is unified by demonstrating the presence of critical drain stress voltage, above which dynamic ON-resistance increases significantly, in different gate stacks. Metal–insulator–semiconductor (MIS)- and Schottky-gated HEMTs show similar dependence of critical voltage on various parameters, which establishes that gate-stack design has negligible impact on the observed phenomena. Furthermore, using the physical insights developed, this work proposes a novel surface passivation scheme to improve the dynamic performance of the device. The proposed surface passivation scheme uses p-type Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Ti <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O (AlTiO), which is deposited over SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> passivation (or GaN cap), and is shown to be an effective tool in improving the dynamic ON-resistance of the device by modulating the electric field in the GaN buffer. The proposed passivation scheme has avoided the critical voltage to appear for the entire drain stress voltage, stress time, and substrate bias range. Detailed computational analysis in conjunction with electroluminescence (EL) and photoluminescence (PL) studies revealed an electric field redistribution due to the p-type nature of AlTiO deposited over the surface passivation/capping layer, which is responsible for relaxed electric field profile in GaN buffer and observed improvement in dynamic performance. Besides, the new observations have further helped to understand the interplay between surface conditions and GaN buffer, defining its collective role in governing the dynamic performance of GaN HEMTs. Finally, various findings and the proposal in this work have been validated for buffers having higher carbon doping and devices with p-type AlTiO deposited over GaN cap instead of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> cap.

Charge trapping in 0.1 μm AlGaN/GaN RF HEMTs: Dependence on barrier properties, voltage and temperature

The goal of this paper is to describe and understand the de-trapping dynamics in AlGaN/GaN transistors for radiofrequency (RF) applications, as a function of three parameters: the aluminium content in the barrier (22.6%, 24.6%, and 26.6%), the stress voltage applied to the drain and temperature. The analysis is based on threshold voltage transient measurements, carried out under at different stress conditions.The original results of this analysis show that: (i) the analysed devices show the presence of a dominant charge-trapping process E1 that, at room temperature, has de-trapping time constants in the range of 10 ms, and activation energy around 0.6 eV. (ii) trap E1 (that is responsible for ~0.5 V threshold voltage shift) is located in the semiconductor material, and its effect increases with increasing aluminium content in the barrier. (iii) leakage measurements indicate that devices with higher Al content in the barrier have a higher gate leakage. Our hypothesis is that under off-state stress, traps in the semiconductor material are charged by electrons injected from the gate metal through defects located in the AlGaN barrier. (iv) a second trap E2, whose signal is independent on the properties of the barrier, was also detected. This trap is supposed to originate from surface defects, is responsible for a minor (~0.1 V) threshold voltage shift and is weakly thermally activated (0.25–0.4 eV). (v) finally, a detailed analysis of the de-trapping kinetics indicated that the signal associated to trap E1 increases linearly with the drain stress voltage, and the related kinetics are ideal exponentials (consistent with semiconductor traps), while the amplitude of trap E2 does not significantly depend on drain voltage, and its kinetics are described by a stretched exponential behaviour (consistent with surface traps).

On the Channel Hot-Electron’s Interaction With C-Doped GaN Buffer and Resultant Gate Degradation in AlGaN/GaN HEMTs

In this work, we report a critical semi- ON-state drain stress voltage above which the gate current increases significantly and degrades permanently in AlGaN/GaN high electron mobility transistors (HEMTs). The observed critical voltage was found to be channel field-dependent by analyzing devices with different field plate lengths and passivation thicknesses, along with different gate–drain distances. Besides field dependence, the critical voltage was found to be carrier energy dependent by comparing the performance of devices subjected to semi- ON-state stress with devices under OFF-state stress. Experimentation on HEMTs with different buffer carbon doping variations revealed the degradation phenomenon to be a function of carbon doping in the GaN buffer. Furthermore, detailed electric field and electron temperature analysis revealed the drain edge to be a hot spot in accelerating interaction of hot electrons with traps in the GaN buffer leading to gate current degradation. A mechanism based on hot electron–buffer trap interaction-induced thermoelastic stress buildup and subsequent defect formation in the GaN buffer is proposed to explain the observed performance degradations. Observations such as a significant rise in channel temperature and accumulation of mechanical stress in the GaN buffer validate the proposed mechanism. Finally, the processes responsible for degradation lead to catastrophic failure of the device for longer stress times by the formation of cracks and pits in the GaN buffer, as validated by the postfailure field emission scanning electron microscopy (FESEM) analysis.

Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors.

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

Various Reliability Investigations of Low Temperature Polycrystalline Silicon Tunnel Field-Effect Thin-Film Transistor

Various reliability issues of low temperature polycrystalline silicon (LTPS) tunnel field-effect transistor (TFET) are comprehensively studied for the first time and compared with conventional LTPS thin-film transistor (TFT). For the positive and negative gate bias stress (P/NGBS) instability, the NGBS causes more serious electrical degradation for both LTPS-TFETs and TFTs because of the higher trap state generation after the NGBS. However, the local P/NGBS near the source-side and drain-side regions show completely different impacts on the LTPS-TFETs and TFTs. The results reveal that the source-side local P/NGBS dominates the entire P/NGBS effects of LTPS-TFETs, and the drain-side local P/NGBS effects have less impacts on the electrical behavior of LTPS-TFETs compared with the entire P/NGBS effects. For the LTPS-TFTs, the local P/NGBS effects show much less electrical degradation than the entire P/NGBS. The difference of local P/NGBS effects between LTPS-TFETs and TFTs is attributed to the different carrier transport mechanisms. In addition to the P/NGBS effects, the hot carrier stress (HCS) with different drain stress voltages is also studied in this work. The drain stress voltage would introduce the horizontal electric field near the junction and reduce the impact of the vertical electric field in the channel region. For the HCS of LTPS-TFETs, the increase of drain stress voltage only leads to the reduction of vertical electric field stress effect but no horizontal electric field stress effect, which is different from the results of LTPS-TFT.

Two-step degradation of a-InGaZnO thin film transistors under DC bias stress

A unified explanation is proposed to consistently explain the two-step degradation of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) under DC positive bias temperature instability (PBTI) stress without or with different drain stress voltages (Vds). For PBTI stress without stress Vds, this initial negative Vth shift is believed to be induced by donor-like defect states corresponding to H2O molecule and intrinsic defects, while for PBTI stress with stress Vds, the negative shift is believed to be induced by donor-like defect states corresponding to oxygen vacancies. The gate-bias-induced electron trapping mechanism is responsible for positive Vth shift. These transitions from negative to positive Vth shift are resulted from the competition between the donor-like states creation and electron trapping.

Degradation analysis and current collapse imaging of AlGaN/GaN HEMTs by measurement of electric field-induced optical second-harmonic generation

On the basis of electric field-induced optical second-harmonic generation (EFISHG) measurements, the degradation of AlGaN/GaN high electron mobility transistor (HEMT) devices was analyzed and the current collapse phenomenon was imaged. Strong second-harmonic (SH) signals were observed at the gate edge at the site of a small defect during the application of a high drain stress voltage (300V), thus indicating that this technique can identify degradation of HEMTs. The EFISHG technique also generated images of the trapped carriers that lead to current collapse in these devices during the on-state. Immediately following the completion of drain-stress voltage application in the off-state (that is, 1μs), SH signals were observed at the gate edge on the drain electrode. This signal location is in good agreement with the well-known virtual gate model of current collapse. The EFISHG measurement technique is therefore capable of detecting pre-breakdown phenomena and producing images of current collapse in AlGaN/GaN HEMT devices.

Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement

Two-dimensional current collapse imaging of a Schottky gate AlGaN/GaN high electron mobility transistor device was achieved by optical electric field-induced second-harmonic generation (EFISHG) measurements. EFISHG measurements can detect the electric field produced by carriers trapped in the on-state of the device, which leads to current collapse. Immediately after (e.g., 1, 100, or 800 μs) the completion of drain-stress voltage (200 V) in the off-state, the second-harmonic (SH) signals appeared within 2 μm from the gate edge on the drain electrode. The SH signal intensity became weak with time, which suggests that the trapped carriers are emitted from the trap sites. The SH signal location supports the well-known virtual gate model for current collapse.

Trend transformation of drain-current degradation under drain-avalanche hot-carrier stress for CLC n-TFTs

Continuous-wave green laser-crystallized (CLC) single-grain-like polycrystalline silicon n-channel thin-film transistors (poly-Si n-TFTs) demonstrate the higher electron mobility and turn-on current than excimer laser annealing (ELA) poly-Si n-TFTs. Furthermore, high drain voltage accelerates the flowing electrons in n-type channel, and hence the hot-carriers possibly cause a serious damage near the drain region and deteriorate the source/drain (S/D) current. In this study, at high drain stress voltage, it appears that CLC TFT was degraded in the initial stress time (before 50 s), but the drain current was enhanced after 50 s. After 50 s stress time, the amount of grain boundary trap states near the drain side was getting large and the reflowing holes damaged the source region or injected into gate oxide near source side as well.

Effects of Hot Carriers on DC and RF Performances of Deep Submicron p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Various Oxide Layer Thicknesses

In this work, the effects of hot carriers on the DC and RF performances of 45 nm p-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with various oxide layer thicknesses were investigated in detail by RF automatic measurements. It was found that a PMOSFET with a thinner oxide layer suffers more serious damage from hot carriers than that with a thicker oxide layer. Also, the greatest degradation occurs at the bias condition when gate stress voltage Vgstr is equal to drain stress voltage Vdstr, and it was found that the degradation of the cutoff frequency fT is dependent on transconductance gm only. This is different from conventional long-channel devices, in which the greatest degradation takes place at Vgstr = Vdstr/2 and when fT is dependent on both gm and the total gate capacitance Cgg (=Cgs+Cgd).

Analysis of hot carrier effects in a 0.35 μm high voltage n-channel LDMOS transistor

This paper presents the results of hot carrier stress experiments of a high voltage 0.35 μm n-channel lateral DMOS transistor. The stress induced degradation was investigated at different ambient temperatures over a wide range of both gate- and drain-stress voltages. In order to explain the observed device degradation under these stress conditions, the combined influence of hole- and electron induced degradation have to be taken into account. A physical explanation of the observed effects is provided and a phenomenological degradation model is suggested.

Evidence for a Composite Interface State Generation Mode in the CHE-Stressed Deep-Submicrometer n-MOSFET

Results from channel hot-electron stressing of 0.18-/spl mu/m n-MOSFETs indicate that, for typical drain stress voltages ranging from 2-3 V, a significant fraction of the Si-SiO/sub 2/ interface states is in fact generated by the majority of the less energetic (/spl les/qV/sub d/<3 eV) electrons in the channel, as opposed to the usual perception that injection of the more energetic (>3 eV) high-energy tail (HET) electrons plays a dominant role. The role of the minority HET electrons, however, becomes increasingly dominant as the drain voltage is reduced. On the basis that the HET electrons gain excess energy through secondary means, this composite interface state generation mode may have a significant impact on the accuracy of hot-carrier reliability projection.

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.