Drain Electrodes Research Articles

Three-dimensional Modeling of Core-structured Field Effect Transistor

Objective: In our previous publication, a core-structured field effect transistor (CoreFET) device shows field effect transistor (FET) behavior. In this work, we investigated factors such as the thickness of the film and the channel on the conductivity of the device in order to optimize the geometry to provide guidance on the fabrication of the device with the best performance. Methods: This study uses Silvaco ATLAS numerical simulation software to investigate the performance of CoreFET. The effects of the thickness of the dielectric layer, SiO2, and the distance between the drain and source (channel length) on the conductivity of the semi-conductor indium gallium zinc oxide (IGZO) have been studied. The flat FET models with the same parameters were used for comparison. Results: Our simulation results demonstrate a directed correlation between the optimized conductivity of the device and the thickness of the dielectric material, as well as the length of the channel. Enhanced sensitivity is achievable by employing a thinner dielectric layer and a narrower channel. Conclusion: According to the results, the device can achieve better performance by optimizing the thickness of the insulator and the gap distance between drain and source electrodes. The remarkable similarity between them indicates that the FET effect remained largely unaffected by variations in FET shape. This observation suggests a consistent outcome across FETs, reinforcing the notion that CoreFET exhibits comparable results as those of film FETs. This finding significantly broadens the scope of CoreFET applications.

Signatures of Topological States in Conjugated Macrocycles.

Single-molecule electrical junctions possess a molecular core connected to source and drain electrodes via anchor groups, which feed and extract electricity from specific atoms within the core. As the distance between electrodes increases, the electrical conductance typically decreases, which is a feature shared by classical Ohmic conductors. Here we analyze the electrical conductance of cycloparaphenylene (CPP) macrocycles and demonstrate that they can exhibit a highly nonclassical increase in their electrical conductance as the distance between electrodes increases. We demonstrate that this is due to the topological nature of the de Broglie wave created by electrons injected into the macrocycle from the source. Although such topological states do not exist in isolated macrocycles, they are created when the molecule is in contact with the source. They are predicted to be a generic feature of conjugated macrocycles and open a new avenue to implementing highly nonclassical transport behavior in molecular junctions.

Source–drain switching characteristics when coupled with a gate-controlled DBD in a microplasma switch

Microplasma switches have attracted considerable attention in harsh environment applications, such as satellites, space exploration, nuclear reactors, and oil drilling, because of their inherent characteristics. A microplasma switch is generally constructed from a source, drain, and gate electrodes, and current conduction is generated between the drain and source (DS), and modulated by the gate. In this work, to improve the gate lifespan and device stability, a microplasma switch with a gate dielectric barrier structure is fabricated due to the even and stable discharge of a dielectric barrier discharge (DBD), and a parameterized nanosecond pulse voltage signal is applied to the gate. Under the effect of the DS voltage, a pulsed DS current is triggered by the gate pulse since a large number of charged particles are generated by the gate DBD, which shows that the DS switching behavior is triggered by the gate pulse. The microplasma switch operates stably (with an average delay jitter of less than 50 ps) at the repetition frequencies (up to 80 kHz). Moreover, the influence of experimental conditions on the switching performance is systematically investigated. The conduction current and delay, which are related to the discharge intensity and speed, are influenced by the electric-field strength of the channel (determined from the pulse amplitude and DS voltage) and its variation rate (determined from the rising and falling edge time of the pulse). In addition, the device performance is influenced by varying the breakdown voltage of the DS (determined from the gas pressure multiplied by DS spacing), which can result in variation of the working coefficient. It is also influenced by varying the wall voltage (decided by pulse width and frequency), which can result in the decrease in the total voltage of the channel.

Boosting the photosensitivity of organic phototransistors with photomultiplication via Corbino configurations

An organic phototransistor (OPT) with a photomultiplication mechanism is studied, where a bulk-heterojunction of C70 and 1,1-bis-(4-bis(4-methyl-phenyl)-amino-phenyl)-cyclohexane is used as a channel and a light-absorbing layer with an Al Schottky contact as source/drain electrodes. The light absorption in the source-side region is found to dominate the photomultiplication effect. In addition, the source electrode area that is up to 100 μm away from the channel is identified as the most effective region in the OPTs with contact-limited operation used in this study. Therefore, to maximize the light-sensing performance of the contact-limited OPTs, we propose Corbino source/drain geometries that have a larger source electrode area than that of the drain electrode. The Corbino-type OPTs show improved photo-response properties proportional to the relative increment of the source-side area, reaching 1.7-fold higher performance in terms of photosensitivity compared to the conventional lateral-type OPTs.

Experimental Characterisation of BGBC OTFT for Indoor CO<sub>2</sub> Gas Sensing

Global warming is a concern nowadays due to excessive release of harmful gasses to the environment, leading to greenhouse effect phenomena worldwide. Based on the data provided by global pollution agencies, the release of greenhouse gasses to the atmosphere is the main cause of pollution and the increase in atmospheric temperature due to warming. Greenhouse gasses (GHGs) contents released to the environment is worrying, with carbon dioxide (CO2) is reported at the highest concentration compared to other gasses. There are many studies conducted to develop and evaluate the performance of harmful gas sensors incorporating inorganic and organic semiconductive materials. Organic semiconductors (OSCs) are environmentally friendly materials, relatively cheaper technology, and comprised of a wide range of materials with good carrier mobility. Therefore, in this work, Organic Thin Film Transistor (OTFT) is developed for gas sensor application. As global warming is becoming more serious, this solution is instead a sustainable solution to the environment, as organic molecules which are held together via Van der Waals bond are easily processed via low-temperature deposition and solution processing as compared to more complicated processes involved in conventional inorganic counterpart. In addition, the developed sensor is generally robust due to the ability to withstand high humidity conditions and can be fabricated on flexible substrates. In this work, suitable materials are identified in basic OTFT construction, which are the electrodes, dielectric and substrate. The scope is mainly focusing on the development of bottom gate OTFT construction, incorporating p-type active material which are Trisisopropylsilylethynyl Pentacene (TIPS Pentacene), Aluminium (Al) as drain and source electrodes, PEDOT: PSS as gate electrode and Polyvinyl alcohol (PVA) as gate dielectric. The materials in bottom gate bottom contact (BGBC) configuration, fabricated via screen printing technique is experimentally tested towards CO2 detection. CO2 is initially detected at 1618 ppm with contact resistance of 15 kΩ, and at 10 ml/minute flow rate, the developed configuration is demonstrated able to achieve sensitivity of 2.069 Ω/ppm. In conclusion, the studied BGBC OTFT has demonstrated suitability and applicability in CO2 gas sensing for sustainable environmental condition monitoring, that could lead to safer environment for the living things on earth. With the proposed dimensions, in the future it is possible to proceed with this work to be fabricated by using more advanced techniques such as photolithography and many others.

Nanoscale Channel Length MoS2 Vertical Field-Effect Transistor Arrays with Side-Wall Source/Drain Electrodes.

Two-dimensional transition metal dichalcogenides (TMDCs) have natural advantages in overcoming the short-channel effect in field-effect transistors (FETs) and in fabricating three-dimensional FETs, which benefit in increasing device density. However, so far, most reported works related to MoS2 FETs with a sub-100 nm channel employ mechanically exfoliated materials and all of the works involve electron beam lithography (EBL), which may limit their application in fabricating wafer-scale device arrays as demanded in integrated circuits (ICs). In this work, MoS2 FET arrays with a side-wall source and drain electrodes vertically distributed are designed and fabricated. The channel length of the as-fabricated FET is basically determined by the thickness of an insulating layer between the source and drain electrodes. The vertically distributed source and drain electrodes enable to reduce the electrode-occupied area and increase in the device density. The as-fabricated vertical FETs exhibit on/off ratios comparable to those of mechanically exfoliated MoS2 FETs with a nanoscale channel length under identical VDS. In addition, the as-fabricated FETs can work at a VDS as low as 10 mV with a desirable on/off ratio (1.9 × 107), which benefits in developing low-power devices. Moreover, the fabrication process is free from EBL and can be applied to wafer-scale device arrays. The statistical results show that the fabricated FET arrays have a device yield of 87.5% and an average on/off ratio of about 1.7 × 106 at a VDS of 10 mV, with the lowest and highest ones to be about 1.3 × 104 and 1.9 × 107, respectively, demonstrating the good reliability of our fabrication process. Our work promises a bright future for TMDCs in realizing high-density and low-power nanoelectronic devices in ICs.

Evaluating the performance of p-type organic field-effect transistor using different source–drain electrodes

Evaluating the performance of p-type organic field-effect transistor using different source–drain electrodes

SiC-based high electron mobility transistor

This paper describes the fabrication of a SiC-based high electron mobility transistor (HEMT). A single-crystal 3C–SiC layer was grown on a C-face 4H–SiC substrate, and 2D electron gas was induced at the 3C–SiC/4H–SiC heterointerface due to the unique polarization physics. The measured Hall mobility of the 2DEG was 586 cm2/V s at room temperature. Source, gate, and drain electrodes were fabricated on the 3C–SiC surface. The drain current for the fabricated SiC-HEMT was measured to be 47.5 mA/mm, and the transconductance was estimated to be 13.5 mS/mm.

Insights into dynamic switching behavior and electric field distribution of depletion-mode GaN HEMT with bonding pad over active layout

Bonding pad over active (BPOA) layout, which stacks traditional horizontal structure pad electrodes vertically above the active area, is an area-effective device architecture and packaging-enabled solution for GaN-based high electron mobility transistors (HEMTs). In this work, the dynamic switching and electric field distribution of such layout, as well as associated capacitance–voltage and trapping characteristics, are comprehensively studied on D-mode GaN-on-sapphire HEMT by performing numerical simulations. In terms of different pad electrodes covering the active area, BPOA is composed of various structures such as gate-related and drain-related BPOAs (i.e. G-BPOA and D-BPOA), among which G-BPOA exhibits inferior switching characteristics due to the additional introduction of Miller capacitance that prolongs the device switching, while breakdown voltage of D-BPOA is 400–900 V lower than other BPOA counterparts due to the interplay between D-BPOA and the drain electrode. Furthermore, the effects of trap capture cross section and trap density on switching characteristics are evaluated. These results highlight the differences in electrical characteristics of various structures within the BPOA layout, and provide valuable insights into BPOA device design and performance improvement.

Extraction of gap states in AlSiO/AlN/GaN metal-oxide-semiconductor field-effect transistors using the multi-terminal capacitance–voltage method

Direct extraction of gap states from a metal-oxide-semiconductor field-effect transistor (MOSFET) in which inversion electrons and holes in a p-type body coexist is challenging. We demonstrate gap-state extraction in lateral-type GaN MOSFETs with high channel mobilities using multi-terminal capacitance–voltage (C–V) methods. The gate stack of the MOSFET was composed of AlSiO/AlN/p-type GaN formed on a p+/n+ GaN tunnel junction structure. The substrate electrode was short-circuited to a p-type body layer through the tunnel junction. The MOSFET was equipped with gate, source, drain, body, and substrate electrodes. When the gate was the high side and the other electrodes were the low side in the AC circuit, a V-shaped C–V curve was obtained because of electron inversion and hole accumulation. When the body/substrate electrodes were connected to the ground level (i.e., split C–V method), the inversion electrons between the gate and source/drain electrodes could be evaluated. We proposed a “reverse” split C–V method in which the source/drain electrodes are grounded and the body/substrate electrodes are connected to the low side. This method enabled extraction of gap states near the valence-band maximum of GaN, with exclusion of the overlap capacitance and the capacitance due to inversion electrons. The proposed method demonstrated overall gap states in the GaN MOSFET with a wide bandgap. The results suggest that hole traps with discrete energy levels caused negative bias instability (NBI) in the GaN MOSFET. Furthermore, NBI and discrete gap states were consistently suppressed by Mg doping at >1018 cm−3 into a p-type body.

Sodium adsorption on nanometer-thick TiO2 channel thin-film transistors for enhanced drain currents

Sodium adsorption on nanometer-thick-TiO2-channel thin-film transistors (TFTs) are examined for enhancing the drain current. In the TFTs, the channel thickness of TiO2 is set as thin as ∼16 nm. The TiO2 film is deposited by atomic layer deposition using plasma excited humified Ar, followed by crystallization into the anatase phase by thermal annealing at 500 °C in air. The gate oxide is a 300 nm thick SiO2 film, which is grown on a highly doped n+ Si substrate. The n+ Si substrate is used as the gate electrode. The drain and source electrodes of Ti are deposited by an electron beam evaporation at room temperature. The TiO2 channel is covered with multiple layers of aluminum silicate and SiO2 films to enhance the Na sorptivity. The multiple films consist of combinations of 1 nm thick SiO2 and 0.16 nm thick aluminum silicate. The channel length and width are 60 and 1000 μm, respectively. The TFT without the Na adsorption exhibits a field effect mobility of ∼0.5 cm2/V s, where the drain current is recorded around 30 μA with a gate voltage of 10 V. With immersion of the TFT in a 10 mM NaCl solution, the drain current is enhanced to the order of mA. The simulation with an equivalent circuit with source and drain resistances suggests that the field effect mobility is enhanced to ∼30 cm2/V s with the adsorption of Na. In this paper, we discuss the operation mechanism of the Na adsorbed TiO2 TFT and its applicability as TFT-based high current switch devices and sensors.

Temperature dependence of hole mobility in methylated germanane field-effect transistor

Methylated germanane, a layered material in which single-layer germanium is terminated by methyl groups, was utilized as a channel material of back-gate-type FETs. Titanium (Ti) and nickel (Ni) were used as source and drain electrodes of FETs, and the FET with the Ti electrode showed ambipolar characteristics, whereas that with the Ni electrode showed p-type characteristics. The maximum hole mobility at RT is 380 cm2V−1s−1, which is higher than those of typical transition metal dichalcogenides. The mobility changes with temperature T according to the T −3/2 law at temperatures ranging from 243 to 343 K, suggesting that the major scattering factor of holes is acoustic phonons.

Effect of source and drain electrode positions on the performance of bottom gate organic thin film transistor

In recent years several novel technologies have emerged on commercial level. Organic electronics is one such technology that has created new avenues for the development of flexible, robust, and cost-effective electronic devices. Transistor developed using organic materials are called organic thin film transistors (OTFT). Transistor is elementary component of any electronic device, any variation in the size or performance of the transistors reflects directly on the overall performance of the electronic devices. Bottom gate bottom contact (BGBC) OTFT is commonly employed single gate organic transistor owing to its simple architecture and easy fabrications. Since in organic semiconductor material carrier mobility of charges is lower, hence its overall performance declines. As a result, its application in electronic circuits becomes limited. Therefore, to enhance the performance of BGBC OTFT and facilitate the optimal charge mobilisation inside organic semiconductor layer i.e., OSC, improvement in the architecture of BGBC is deemed necessary. In this research article the performance of BGBC OTFT is analysed for different positions of electrodes viz. source and drain embedded inside the OSC layer. The study signifies the effect of electrode positions on performance optimization of BGBC OTFT without changing the materials, dimensions, or the operating voltage regime. It has been found that for 30 nm thick OSC layer, the electrodes should ideally be placed between 5 nm to 10 nm above the junction of OSC and dielectric layer inside OSC layer for optimal results.

Study on the single-event burnout mechanism of GaN MMIC power amplifiers

In this Letter, a single-event burnout (SEB) mechanism in gallium nitride (GaN) microwave monolithic integrated circuit power amplifiers with a high linear energy transfer of 78.1 MeV·cm2/mg has been investigated in detail. A typical SEB phenomenon was observed. With the aid of photon emission measurements and scanning electron microscopy, it is found that catastrophic burnout occurs in the power-stage GaN high electron mobility transistors (HEMTs) and the metal–insulator–metal (MIM) capacitors, respectively. For the GaN HEMT, the incident heavy ions will generate electron–hole pairs within it, which can gain enough energy with the transverse high electric field. The high-energy electrons will collide with the lattice near the drain electrode and induce significant electron trapping, which will result in a significant longitudinal local electric field. When a critical electric field is achieved, catastrophic burnout occurs. For the MIM capacitor, the burnout is attributed to the single-event dielectric rupture via severe impact ionization or latent tracks when heavy ions strike it.

High sensitivity saliva-based biosensor in detection of breast cancer biomarkers: HER2 and CA15-3.

The prevalence of breast cancer in women underscores the urgent need for innovative and efficient detection methods. This study addresses this imperative by harnessing salivary biomarkers, offering a noninvasive and accessible means of identifying breast cancer. In this study, commercially available disposable based strips similar to the commonly used glucose detection strips were utilized and functionalized to detect breast cancer with biomarkers of HER2 and CA15-3. The results demonstrated limits of detection for these two biomarkers reached as low as 1 fg/ml much lower than those of conventional enzyme-linked immunosorbent assay in the range of 1∼4 ng/ml. By employing a synchronized double-pulse method to apply 10 of 1.2 ms voltage pulses to the electrode of sensing strip and drain electrode of the transistor for amplifying the detected signal, and the detected signal was the average of 10 digital output readings corresponding to those 10 voltage pulses. The sensor sensitivities were achieved approximately 70/dec and 30/dec for HER2 and CA15-3, respectively. Moreover, the efficiency of this novel technique is underscored by its swift testing time of less than 15 ms and its minimal sample requirement of only 3 μl of saliva. The simplicity of operation and the potential for widespread public use in the future position this approach as a transformative tool in the early detection of breast cancer. This research not only provides a crucial advancement in diagnostic methodologies but also holds the promise of revolutionizing public health practices.

Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed.

A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (VF) at IS = 100 A/cm2, which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (Emox). Additionally, the gate-drain capacitance (Cgd) and gate-drain charge (Qgd) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater Ron,sp than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.

Magnetoconductance from spin-charge inter-conversion in two-terminal molecular nanojunctions with strong spin-orbit coupling electrodes.

Spin-charge inter-conversion mediated by spin-orbit coupling can lead to finite magnetoconductance in two-terminal molecular nanojunctions under non-equilibrium conditions. Here, we demonstrate how such a finite magnetoconductance can emerge in model two-terminal molecular nanojunctions by means of density functional theory based transport calculations with spin-orbit coupling in a first-order perturbation approximation. The junctions are built from the two chiral partners of an idealized helical molecule and tungsten or gold electrodes with two layers of magnetic nickel at the interface of the drain electrodes. Using Au source electrodes and a low applied bias of 0.1 V, we find percentage relative magnetoconductance values in excess of the lower bound reported in recent low-temperature, low-bias, experiments. The left-handed molecule is seen to exhibit greater magnetoconductance than its right-handed chiral partner for both Au and W source electrodes, thus demonstrating that our calculations can also exhibit enantioselectivity.

Bias-independent subthreshold swing in ballistic cold-source field-effect transistors by drain density-of-states engineering

Low power consumption and stable performance insensitive to power supply are highly required for field-effect transistors integrated in portable technologies. Here, we report a mechanism of bias-independent sub-60 mV/dec subthreshold swing (SS) in ballistic cold-source field-effect transistors (CS-FETs) for portable electronics. Our first-principles and quantum-transport simulations demonstrate that, in the ballistic-transport regime, the energy alignment of the number of conduction modes (NOCM) between the drain and source electrodes is critical to achieving bias-independent SS of C31/MoS2-based CS-FETs. By revealing the connection between NOCM and density of states (DOS), we propose a device model to demonstrate how similar slopes of the NOCM and DOS in the drain falling into the gate window can stabilize the SS of the devices under different bias. This study underscores the significance of drain DOS engineering in the design of bias-insensitive CS-FETs for portable electronic applications.

Intense pulsed light annealing of solution-based indium–gallium–zinc–oxide semiconductors with printed Ag source and drain electrodes for bottom gate thin film transistors

In this study, an intense pulsed light (IPL) annealing process for a printed multi-layered indium–gallium–zinc–oxide (IGZO) and silver (Ag) electrode structure was developed for a high performance all-printed inorganic thin film transistor (TFT). Through a solution process using IGZO precursor and Ag ink, the bottom gate structure TFT was fabricated. The spin coating method was used to form the IGZO semiconductor layer on a heavily-doped silicon wafer covered with thermally grown silicon dioxide. The annealing process of the IGZO layer utilized an optimized IPL irradiation process. The Ag inks were printed on the IGZO layer by screen printing to form the source and drain (S/D) pattern. This S/D pattern was dried by near infrared radiation (NIR) and the dried S/D pattern was sintered with intense pulsed light by varying the irradiation energy. The performances of the all-printed TFT such as the field effect mobility and on–off ratio electrical transfer properties were measured by a parameter analyzer. The interfacial analysis including the contact resistance and cross-sectional microstructure analysis is essential because diffusion phenomenon can occur during the annealing and sintering process. Consequently, this TFT device showed noteworthy performance (field effect mobility: 7.96 cm2/V s, on/off ratio: 107). This is similar performance compared to a conventional TFT, which is expected to open a new path in the printed metal oxide-based TFT field.

Ultraflexible Monolithic Three-Dimensional Static Random Access Memory.

Flexible static random access memory (SRAM) plays an important role in flexible electronics and systems. However, achieving SRAM with a small footprint, high flexibility, and high thermal stability has always been a big challenge. In this work, an ultraflexible six-transistor SRAM with high integration density is realized based on a monolithic three-dimensional (M3D) design. In this design, vertical stacked n-type indium gallium zinc oxide thin film transistors and p-type carbon nanotube transistors share common gate and drain electrodes, respectively, saving interlayer vias used in traditional M3D designs. This compact architecture reduces the footprint of the SRAM cell from a six-transistor to a four-transistor area, saving 33% of the area, and significantly enables the SRAM to have the highest flexibility among the reported ones, withstanding a harsh deforming process (6000 cycles of bending at a radius of 500 μm) without performance degradation. Moreover, this design facilitates the thermal stability of the SRAM under high temperature (333 K). It also exhibits great static and dynamic performance, with the highest normalized hold noise margin of 73.6%, a maximum gain of 151.2, and a minimum static power consumption of 3.15 μW in hold operation among the reported flexible SRAMs. This demonstration provides possibilities for SRAMs to be used in advanced wearable system applications.