Drain Electric Field Research Articles

Output breakdown characteristics of amorphous InGaZnO thin-film transistors at high gate voltage

Output characteristics of top-gate amorphous InGaZnO thin-film transistors are investigated at high gate voltage. With the increasing drain voltage, an output breakdown crops up closely following a drastic uprush of drain current. Such dramatically elevated drain current derives from the self-heating (SH) effect-generated channel donors. Measured at different high gate voltages, the output breakdown occurs in either linear or saturation regime, respectively, corresponding to normally-on and normally-off transfer curve, while the SH-triggering powers are almost identical. The conductor-like channel originates from the SH-induced high donor population, while the disconnection between channel and drain is caused by a highly defective region near drain, where the hot-carrier damage is violently activated by the SH-induced high temperature and the high drain electric field in saturation regime.

Assessment of the Biosensing Capabilities of SiGe Heterojunction Negative Capacitance-Vertical Tunnel Field-Effect Transistor.

In this study, a comparison of the negative capacitance vertical tunnel field-effect transistor (NC-VTFET) and VTFET for biosensing applications was conducted. Dielectrically modulated TFET demonstrates better sensitivity than the traditional metal oxide field effect transistor as a biosensor in label-free biosensing applications. The TFET biosensor, however, has much room for advancement by enhancing its DC characteristics. This research addresses the impact of ferroelectric gate oxide for integration of negative capacitance (NC) effect with the SiGe heterojunction pocket at the source-channel junction to enhance performance for biosensor applications. By putting the NC layer over SiO2, the channel voltage increases with decreased subthreshold slope and OFF current, thereby creating an NC effect. Because SiGe has a narrow band gap, pocket doping of SiGe near the source channel junction will increase the concentration of charge carriers, improving the band-to-band tunneling. In order to aid in the integration of biomolecules and to modulate band-to-band tunneling based on charge density (qf), dielectric constant (k), temperature, and cavity length, a cavity is additionally inserted above the source channel junction and underneath the NC layer, near to SiO2. These values were compared with and without the incorporation of NC layer with respect to various electrical properties such as drain current (Id), sensitivity, and electric field (E). According to the findings, labeled and label-free biosensors' sensitivity may be increased by incorporating the NC effect into VTFET biosensors.

Drain Current and Transconductance Analysis of GaN GAA Nanowire FET with High K Dielectric

This paper presents the GaN GAA nanowire FET analysis with high K dielectric. The new phase in the development of power semiconductor devices has begun with the introduction of the outstanding benefits of employing wide bandgap semiconductors like gallium nitride (GaN) in the development of sophisticated devices. This work has been carried out to evaluate drain current, electric field, electric potential, and transconductance with SiO2 and HfO2 as dielectric. There are several advantages of switching from silicon-based circuits to GaN-based ones The drain current analysis shows that the device with HfO2 gate dielectric has a higher ON/OFF ratio compared to the device with SiO2 gate dielectric. The transconductance analysis also shows that the device with HfO2 gate dielectric has a higher transconductance value of approximately 9.88 S compared to the device with SiO2 gate dielectric.

Simulation analysis of electrical characteristics of P-gate enhanced HEMT with C-doped buffer layer

The C-doped P-gate-enhanced HEMT (PEHEMT) is simulated by using the Silvaco T-CAD tool. The interaction among the C acceptor trap, electron, and hole in the buffer layer at different voltages promotes interesting electrical characteristic within the device. In off-state conditions, the peak electric field position shifts from the edge of gate to the edge of drain. During the process of peak electric field transfer, the gate electric field gradually saturates, and the increase rate of peak electric field shows a turning point at 350 V (Vd < 600 V). As the voltage further increases (Vd > 600 V), the increase rate of the drain electric field gradually slows down and tends to saturation, and the corresponding saturated gate electric field begins to increase. The uniform, quasi-linear, and step distributions of three different C acceptor in the buffer layer exhibit different degrees of current collapse under 1 ms bias stress, with values of 21.8%, 12.7%, and 12.8%, respectively. In this work, we have provided appropriate explanations for the above phenomena.

Characteristics of Offset Corbino Thin Film Transistor: A Physical Model

Offset Corbino thin film transistor is a good candidate for high voltage thin film transistor (HVTFT) due to the uniform drain electric field distribution benefiting from the circular structure. The physical model of offset Corbino thin film transistor characteristics has yet to be clarified. In this study, Equations are derived to describe the current–voltage relations of Corbino TFT with offset at the drain or source sides. The influence of offset position and parameters on the saturation voltage and the saturation current was described quantitatively. Three-dimensional Computer-Aided Design simulation and experiment results verify the theoretical physical model. Our physical model provides design rules for high voltage offset Corbino TFT when considering the voltage tolerance and saturation current balance.

Design and Parametric Analysis of Charge Plasma Junctionless TFET for Biosensor Applications

This paper presents a new design of charge plasma junctionless tunnel field effect transistor (CP JLTFET) with improved ON current, surface potentials. For the ease of fabrication, source and drain regions are induced in intrinsic silicon material using proper metal workfunctions. The rate of tunneling of electrons is found more in case of proposed CP JLTFET. The cavity length is varied between 8 nm and 10 nm and different dielectric constants have been used. This increased the ON state performance of device i.e ON drive current, potential and electric field. The increase in tunneling of electrons is mainly due to high recombination of carriers in the channel region. The proposed device simulated their electrical parameters like drain current, surface potentials, electric field, and energy bands with different dielectric constants. These excellent performance parameters of the proposed device with an appropriate material can be used for sensing application of biomolecules by introducing a cavity in the device.

Tunnel-FET Evolution and Applications for Analog Circuits

In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analog application the intrinsic voltage gain (AV) is the most important one. For the early generations, that are based on silicon, the SS does not reach values smaller than 60mV/dec at room temperature, however, the AV reaches values up to 80 dB, showing to be promising for analog applications. As the TFETs were being optimized for digital applications and consequently presenting better switching performance, the intrinsic voltage gain moves in the opposite direction. This opposite trend is related to which transport mechanism is predominant for each type of device. While III-V TFETs are more dependent on Band to Band Tunneling (BTBT), silicon devices are more relying on Trap-Assisted Tunneling (TAT). While BTBT allows for faster switching, TAT is less dependent on the drain electric field, so the former favors SS while the latter favors AV. Based on the good analog behavior of silicon channel TFETs, a two-stage operational transconductance amplifier (OTA) was designed with different TFET technologies and the compared results were discussed.

Influence of GaN/ZrO2 interfacial layer defects on 8-nm GaN-SOI-FinFET for reliable RFIC design

This work presents, the reliability of GaN/ZrO2 (Gallium Nitride/Zirconium dioxide) interfacial layer defects on 8-nm Gallium Nitride (GaN) Silicon-on-Insulator (SOI) FinFET (GaN-SOI-FinFET). Positive, negative, and neutral interface trap charges are considered in all the results and simultaneously compared with SOI-FinFET with an 8-nm gate length for the evaluation of device reliability. It is found that the proposed device is more immune to interfacial trap defects and reflected in terms of drain current (Id), device efficiency (gm/Id), transconductance (gm), subthreshold slope (SS), electric field, surface potential, and threshold voltage at an ultra-low voltage (VDS = 0.1 V). Further, the performance degradation of GaN-SOI-FinFET is calculated by various linearity figures of merits (FOMs) such as higher-order transconductance coefficients (gm2 and gm3), voltage, and current intercept points (VIP2, VIP3, and IIP3). Moreover, device reliability is also performed by evaluating intermodulation and harmonic distortions (IMD3, HD2, and HD3). The proposed device shows better reliability in the presence of interfacial traps and paves the way for high-performance low power, high linearity, and lesser harmonic distortions performance for RFIC design.

Analog performance of GaN/AlGaN high-electron-mobility transistors

In this paper, the analog properties of advanced GaN/AlGaN High-Electron-Mobility Transistors (HEMTs) are studied as a function of temperature (T). The drain current, the threshold voltage, the transconductance and the output conductance are experimentally investigated under saturation operation. Moreover, important figures of merit for the analog performance, such as transconductance-over-drain current, Early voltage and intrinsic voltage gain are analyzed for different channel lengths in the temperature range of 25 °C till 200 °C. The results indicate that due to change in the Fermi potential, the analog parameters reduce with increasing T. Furthermore, the performance increase for longer channel devices is correlated directly with the lower drain electric field penetration.

A Charge Plasma Based Label Free Biomolecule Detector Using SiGe-Heterojunction Double Gate Tunnel FET

To overcome the random dopant fluctuations (RDFs) and high thermal budget problems faced by normally doped Tunnel Field Effect Transistor (TFET) devices, charge plasma SiGe-heterojunction double gate TFET is utilized to design a label free biosensor. The performance of proposed biosensor is analyzed for different values of dielectric constant (k), charge density (both positive and negative), gate work function and cavity dimensions. These parameters alter the electric properties of the biosensor which help in the detection process. Their effect on the drain current, electric field, surface potential, sub-threshold swing (SS), ION/IOFF ratio, and electron tunneling rate (ETR) of the device is also discussed. Furthermore, the drain current sensitivity of the proposed biosensor is analyzed and it is found that a maximum sensitivity of 1.13 × 1010 is obtained for dielectric constant k = 12. The proposed biosensor is implemented by carrying out two-dimensional device simulations using the Silvaco ATLAS tool.

Effect of Source–Drain Electric Field on Charge Transport Mechanism in Polymer‐Based Thin‐Film Transistors

Donor–acceptor copolymer‐based field‐effect transistors (FETs) have attracted considerable attention from technological and academic perspectives due to their low band gap, high mobility, low cost, and easy solution processability, flexibility, and stretch ability. Among different solution‐processing techniques, meniscus‐guided coating has the potential for large‐area film formation. Moreover, 29‐diketopyrrolopyrroleselenophene vinylene selenophene (29‐DPP‐SVS) donor‐acceptor copolymer‐based FETs have already exhibited excellent performance due to their short π–π stacking distance and strong π–π interaction. Charge carrier mobility of these types of semiconducting materials is significantly dependent on the applied electric field. Therefore, detailed analysis of the electric‐field dependency of charge carrier mobility is necessary to understand the transport mechanisms within these materials. Thus, herein, 29‐DPP‐SVS‐based FETs are fabricated by varying the blade‐coating speed of their semiconductor layer. Then, the effect of the blade‐coating speed on the electrical properties of the FETs is studied through the analysis of electric‐field‐dependent mobility. The results suggest that the charge carrier mobility of different FETs is dependent on the applied electric field and that the type of dependency is Poole–Frenkel. At an optimized blade‐coating speed (2 mm s−1), the device exhibits maximum zero‐field mobility (3.39 cm2 V−1 s−1) due to the low trap density within the conducting channel.

A CMOS-MEMS Accelerometer With U-Channel Suspended Gate SOI FET

There have always been demands for the development of microscale sensors with integrated miniature electronics circuitry. Requirement of external amplification for the conventional MEMS accelerometer poses limitation on scaling, design, fabrication and on-chip Integrated Circuit (IC) compatibility. These limitations could be surpassed by the implementation of integrated CMOS-MEMS architectures for sensors and actuators. Here a novel U-channel suspended gate silicon on insulator field effect transistor (USG-SOIFET) is proposed to circumvent the pseudo short channel effects (P-SCE) present in the suspended gate field effect transistor (SGFET). In the proposed USG-SOIFET, the source and drain are separated by an air-gap and thereby ensuring effective screening of drain electric field penetration into source region. The gate length (L) of USG-SOIFET is 4 times lower than the conventional planar channel SGFET for the same performance of the device. Since the same performance is achieved with a smaller length, this results in a smaller device. Finite Element Modeling (FEM) of USG-SOIFET z-axis accelerometer using CoventerMP1.3 and TCAD process, device modeling and simulation of the USG-SOIFET using Synopsys Sentaurus are presented here. The sensitivity of the accelerometer is 4.185 μA/g with a non-linearity of 4.96% for ± 5 g detection range. The bandwidth of the accelerometer is 100 Hz and the cross-axis sensitivity is found to be 3.52%. A fabrication process integration scheme for realizing USG-SOIFET has also been discussed along with process simulation to demonstrate the feasibility of realizing this new device architecture. This device platform is a potential candidate for monolithic integration with CMOS.

Raised Source/Drain (RSD) and Vertical Lightly Doped Drain (LDD) Poly-Si Thin-Film Transistor

The raised source/drain (RSD) structure is one of thin film transistor designs that is often used to improve device characteristics. Many studies have mentioned that the high impact ionization rate occurring at a drain side can be reduced, owing to a raised source/drain area that can disperse the drain electric field. In this study, we will discuss how the electric field at the drain side of an RSD device is reduced by a vertical lightly doped drain (LDD) scheme rather than a RSD structure. We used different raised source/drain forms to simulate the drain side electric field for each device, as well as their output characteristics, using Integrated Systems Engineering (ISE-TCAD) simulators. Different source and drain thicknesses and doping profiles were applied to verify the RSD mechanism. We found that the electric fields of a traditional device and uniform doping RSD structures are almost the same (~2.9 × 105 V/cm). The maximum drain electric field could be reduced to ~2 × 105 V/cm if a vertical lightly doped drain RSD scheme was adopted. A pure raised source/drain structure did not benefit the device characteristics if a vertical lightly doped drain design was not included in the raised source/drain areas.

Field-effect pump: liquid dielectrophoresis along a virtual microchannel with source-gate-drain electric fields.

We investigate liquid dielectrophoresis (LDEP) to implement field-effect pumps (FEPs) that drive liquids from source, via gate, toward drain electric fields between parallel plates without external pumps or the problem of dead volume. The appropriate gate electric field establishes a wall-less virtual microchannel to transfer the liquid from source to drain with an adjustable flow rate (Q) controlled by the difference of the square of the electric field strength (ΔE2DS). Analogous to field-effect transistors (FETs), the FEPs can operate in a "linear", "transition" or "saturation" region depending on ΔE2GD and ΔE2DS. With a sufficient ΔE2GD and a small ΔE2DS, the FEPs operated in the linear region where Q was linearly proportional to ΔE2DS and inversely proportional to the flow resistance R that was mainly determined by the length (L), width (W) and height (H) of a stable and fully-occupied virtual microchannel. With an insufficient ΔE2GD and a moderate to large ΔE2DS, narrowing, tapering and even pinch-off of virtual microchannels were observed, which increased R and changed the operation into the transition or saturation region. A field-effect stream merger regulating two streams was built based on two FEPs with shared gate and drain electrodes. The versatility of FEPs was demonstrated with preliminary studies on whole blood and particle solutions.

Design and investigation of the double gate TFET with heterogeneous gate dielectric using different gate materials

A 2 dimensional model of double gate hetero dielectric Tunnel Field Effect Transistor (HD-DG TFET) with hetero dielectric gate stack is carved with Silicon dioxide (SiO2) and Hafnium dioxide (HfO2) as dielectric materials. The electrical characteristics are demonstrated for the device by using 2D numerical device simulator Silvaco TCAD. The channel length, doping concentration of drain and source, thickness of device and effective oxide layer thickness of the device is kept constant throughout the work. It is showed that the proposed structure has better performance than Double Gate TFET. Also gate materials used are silver, gold, platinum and Npolysilicon. By using these materials Drain current and electric field of the device has been plotted. Also the proposed model shows a lower leakage current, better ION/IOFF ratio sub-threshold swing and lower DIBL. It has also been remarked that use of metal gate with appropriate work function along with high-k and hetero dielectric improves the carrier transport in the channel. This model aims to lower the short channel effects and give emphasis to improvement of switching ratio.

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

This paper presents an analysis of the silicon film thickness (6 nm and 14 nm), the gate dielectric material (SiO2 and High- κ material) and the Ground Plane influence on the analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices, based on experimental and simulation results. Two channel lengths (70 nm and 1μm) have been considered and the analog performance has been analyzed as a function of the back gate bias. It is shown that at zero back gate bias , the presence of a Ground Plane improves the transconductance in the saturation region due to the strong coupling between front and back gates in devices with a long channel (1 μm), thin silicon film (6 nm) and SiO2 as gate dielectric material. However, for the intrinsic voltage gain, output conductance and Early Voltage, the devices without Ground Plane present better results due to the higher drain electrical field penetration. Short-channel transistors (70 nm) with Ground Plane show an improvement of the analog parameters also due to the high drain electrical field penetration. Similar behavior is noticed in devices with a thicker silicon film (14nm). UTBB nMOSFETs with High- κ material present less influence of a Ground Plane on the parameters analyzed. Varying the back gate bias in devices with long channel (1 μm) and SiO2 as gate dielectric material, the analog parameters present better results in devices without Ground Plane, except for the transconductance in long channel transistors with a thin silicon film, for the reason explained before (strong coupling between front and back gates). Devices with High-κ material as gate dielectric show a minor improvement of the analog performance with a Ground Plane.

Drain induced barrier increasing in multilayer ReS2

The interlayer tunneling resistivity (Rint) and Thomas-Fermi charge screening effects play critical roles in the carrier transport of two-dimensional (2D) multilayer devices. For example, the vertical electric field modifies the Rint, resulting in a channel migration along the c-axis. However, because Rint varies considerably with the drain electric field in addition to the vertical field, the effective contribution of each layer to the total current varies with the drain bias (VD). Here, we demonstrate a drain induced barrier increasing (DIBI) in 2D multilayer rhenium disulfide (ReS2) as a possible reverse short channel effect (rSCE). The reported decoupled layer interaction and much higher interlayer resistivity of ReS2 compared to other 2D materials allow us to observe the DIBI clearly. As VD increases, the effective amplitude of Rint decreases dramatically, leading to (i) the increase of off-current, (ii) the enhancement of field-effect mobility, and (iii) the blue shift of the flat band voltage (VFB), which is in sharp contrast to a previous report on a short-channel bulk-Si device with drain induced barrier lowering (DIBL). We attribute this difference to the weakened Fermi level (EF) tunability when the channel migrates from the bottom to the top surface of ReS2, and to an opposite electrostatic force resulting from VD, implying the increased importance of VD-dependent Rint in the carrier transport mechanism of 2D multilayer systems. The VD-dependent Coulomb scattering parameter probed via a low frequency (LF) noise analysis provides deeper insights for the channel shift. Our findings pave the way for understanding and exploiting the fundamental charge transport mechanism in 2D multilayer systems.

Modelling and Simulation of Hetero-Dielectric Surrounding Gate TFET

Analytical modelling for a tri material cylindrical gate tunnel FET is developed in this paper. Poisson equation and parabolic approximation technique are employed to develop the analytical model of the proposed device. Inorder to eliminate the influence of short channel effects and the leakage current, a surrounding gate with three different work function materials is used. Stacked dielectric or hetero-dielectric is used to improve the ON current of device. Performance of the device has been analyzed with different gate material lengths such as 10 nm, 15 nm and 20 nm. The developed 2-D mathematical model is used to obtain results like drain current, surface potential and electrical field in the vertical and lateral direction. From the results, a reduction in the device limitations is inferred and the leakage current is also considerably reduced. It has been found from the presented results that the proposed device structure Tri Material Cylindrical Gate Tunnel FET (TM CG TFET) provides the improved ON state current (10-3A/µm) and reduced OFF state current (10-14A/µm). The accuracy of the results and characteristics of the device are evaluated using TCAD simulations.

Inhibiting the Kink Effect and Hot-Carrier Stress Degradation Using Dual-Gate Low-Temperature Poly-Si TFTs

This study examines the appearance of a kink effect phenomenon in the I $_{\mathbf {D}}$ -V $_{\mathbf {D}}$ electrical characteristics of low-temperature polycrystalline Si thin-film transistors (LTPS TFTs) after high-current-induced hot-carrier stress (HCS). During HCS, electron–hole pairs were generated in the channel near the drain terminal owing to impact ionization. Next, the electrons were repelled towar the source by the drain electric field, thereby inducing the floating body effect, which lowered the source barrier. In addition, a dual-gate-structured LTPS was found to inhibit the electrical degradation caused by HCS. The COMSOL simulation indicated that in the dual-gate structure, holes at the upper and lower margins of the channel were inverted and inhibited the degradation caused by the floating body effect. Therefore, the use of dual-gate LTPS TFTs could facilitate high-current gate-on-array circuit applications in display panels.

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field.