Drain Efficiency Of Power Amplifier Research Articles

A 0.3-to-1-GHz IoT Transmitter Employing Pseudo-Randomized Phase Switching Modulator and Single-Supply Class-G Harmonic Rejection PA

A wideband Internet of Things (IoT) transmitter (TX) employing open-loop binary frequency-shift keying (BFSK) modulator with a pseudo-randomized phase transition (PRPT) time and a single-supply Class-G harmonic rejection (HR) power amplifier (PA) is presented. The proposed open-loop phase switching modulator eliminates the data-rate limitation in a conventional phase-locked loop (PLL)-based closed-loop modulator, while the PRPT scheme increases the effective phase resolution with a better power efficiency than delta–sigma modulation (DSM)-based randomization. Thus, a low spur level below −40 dBc is achieved with only a 4-bit phase resolution. The Class-G HR PA, including a four-level supply voltage waveform generator, is proposed as a high-efficiency and low spurious PA architecture. The proposed HR PA presents the third- and fifth-harmonics cancellation over the 0.3-to-1-GHz band, while only a single supply is required for Class-G implementation of the HR PA. The proposed BFSK TX is implemented in a 55-nm CMOS process. Measured with a 0.3-to-1-GHz continuous-wave carrier, TX output power and PA drain efficiency are 2.7 ± 0.2 dB and 52% ± 3%, respectively, operating from a 0.9-V supply. The HRs of −31.4/−42.7 and −28.2/−42.4 dBc at the third/fifth harmonics are measured at the lowest (0.3 GHz) and the highest (1 GHz) carrier frequencies, respectively. With a data rate of 1 Mb/s, the measured FSK errors are 3.6% and 4.2% at both ends of the operating frequency.

An X-Band Class-J Power Amplifier With Active Load Modulation to Boost Drain Efficiency

In this paper, the performance of the class-J mode power amplifier (PA) is studied when an auxiliary network performs active load modulation on the main transistor. Load modulation is realized by injecting an additional class-C like current with conduction angle of $\alpha $ to the drain node of the main transistor. The injected current employs a phase shift of $\phi $ with respect to the half-sinusoidal current of the main transistor, and its maximum value is tuned with the size of the transistor used in the auxiliary network. Detailed theoretical formulations are presented for the optimal load impedances of the PA at the fundamental and second-harmonic frequencies. Furthermore, the output power and drain efficiency of the PA are derived, and it is shown that the drain efficiency of the proposed PA can be as high as 96.8% in theory. The optimal values of $\alpha $ and $\phi $ for improving the drain efficiency of the load-modulated class-J PA are obtained, and a design methodology is also proposed to choose the optimal size of the transistor employed in the auxiliary network. To verify the theoretical derivations, a proof-of-concept 0.83 W class-J PA was designed and fabricated in a 0.25 $\mu \text{m}$ GaAs pHEMT process. The designed PA occupies 3.19 mm2 die area, and it achieves 71% drain-efficiency and 50% power-added-efficiency at 10 GHz.

A CMOS 1.2-V Hybrid Current- and Voltage-Mode Three-Way Digital Doherty PA With Built-In Phase Nonlinearity Compensation

This article presents a fully integrated hybrid current- and voltage-mode three-way digital Doherty power amplifier (PA) in CMOS using a single supply with builtin large-signal phase nonlinearity compensation. The nonlinear phase responses in both current-mode digital PA (C-DPA) and voltage-mode digital PA (V-DPA) are theoretically analyzed, which are further leveraged to achieve the PA nonlinear phase compensation. To the best of our knowledge, it is the first time the amplitude modulation (AM)-phase modulation (PM) response in V-DPA is explained in detail. The PA exploits the lagging AM-PM distortion of C-DPA and leading AM-PM distortion of V-DPAs, resulting in built-in large-signal phase nonlinearity cancellation without phase pre-distortion. Moreover, the transformer-based Doherty output network provides active load modulation to both C-DPA and V-DPA, achieving a three-way Doherty PA for deep power back-off (PBO) efficiency enhancement without supply modulation. Finally, the 1.2-V single power supply for PA power cells and input drivers reduces supply complexity. As a proof-of-concept, the hybrid three-way digital Doherty PA is implemented in a 45-nm CMOS SOI process. The measurements show a 38.5% peak drain efficiency (DE), 22.4-dBm saturated output power (Psat), and 32.1%/18.7% DE at 3.4-/9.3-dB PBO, achieving ×1.25/×1.46 PBO efficiency enhancement over idealistic class-B PA PBO efficiency at 2.3 GHz. The measured AM-PM distortion is 4.7° which is state-of-the-art among DPAs with PBO efficiency enhancement. The hybrid digital Doherty PA supports 40-/10-MSym/s 64-quadrature amplitude modulation (QAM)/256-QAM at 15.3-/15.2-dBm average output power and 24.7%/23.2% average PA DE while maintaining error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) lower than -32/-32.1 dB and -30.6/-28.9 dBc without phase pre-distortion.

An RF-Powered DLL-Based 2.4-GHz Transmitter for Autonomous Wireless Sensor Nodes

This paper presents the system and circuit design of a compact radio frequency (RF)-powered 2.4-GHz CMOS transmitter (TX) to be used for autonomous wireless sensor nodes (WSNs). The proposed TX utilizes the received dedicated RF signal for both energy harvesting as well as frequency synthesis. A TX RF carrier is derived from the received RF signal by means of a delay locked loop and XOR-based frequency multiplier. The 50- $\Omega $ load is subsequently driven by a tuned switching RF power amplifier (PA) with 25% duty cycle input for high global efficiency. The design is fabricated in 40-nm CMOS technology and occupies a die area of 0.16 mm2. Experimental results show a rectifier with 36.83% peak efficiency and power management circuit with 120-nA current consumption that enables a low start-up power of −18.4 dBm. The TX outputs a continuous 2.44-GHz RF signal at −2.57 dBm with 36.5% PA drain efficiency and 23.9% global efficiency from a 915-MHz RF input and supports ON–OFF keying modulation.

Energy-Efficiency of Millimeter-Wave Full-Duplex Relaying Systems: Challenges and Solutions

Full-duplex (FD) relaying is a promising solution for fifth generation (5G) wireless communications due to its potential to provide high spectral efficiency (SE) transmission. However, FD relay nodes consume much higher power than half-duplex relay nodes, especially in millimeter (mm)-wave band. Therefore, energy-efficiency (EE) is an important issue to address for mm-wave FD relaying systems, which highlights the green evolution of 5G wireless communications. Existing FD relaying related research is SE-oriented, which is not efficient in cutting carbon footprint. This particle is different in that it addresses the critical EE challenges in implementing FD relaying in mm-wave systems, including low drain efficiency of power amplifier, high circuit power consumption, and additional power required by FD relays to mitigate self-interference. Based on the features of mm-wave communications, we outline a number of promising EE-oriented solutions for designing FD relaying enabled systems, including adaptive self-interference cancellation, transmission power adaptation, hybrid relaying mode selection, multi-input-multi-output (MIMO), and massive MIMO FD relaying. Some EE-oriented future research is also envisaged for mm-wave FD relaying systems.

Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS

This paper presents a digital polar Doherty power amplifier (PA) fully integrated in a 65 nm bulk CMOS process. It achieves +27.3 dBm peak output power and 32.5% peak PA drain efficiency at 3.82 GHz and 3.60 GHz, respectively. The proposed digital Doherty PA architecture optimizes the cooperation of the main and auxiliary amplifiers and achieves superior back-off efficiency enhancement (a maximum 47.9% improvement versus the corresponding Class-B operation). This digital intensive architecture also allows in-field PA reconfigurability which both provides robust PA operation against antenna mismatches and allows flexible trade-off optimization on PA efficiency and linearity. Transformer-based passives are employed as the Doherty input and output networks. The input 90 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> signal splitter is realized by a 6-port folded differential transformer structure. The active Doherty load modulation and power combining at the PA output are achieved by two transformers in a parallel configuration. These transformer-based passives ensure an ultra-compact PA design (2.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and broad bandwidth (24.9% for -1 dB P out bandwidth). Measurement with 1 MSym/s QPSK signal shows 3.5% rms EVM with +23.5 dBm average output power and 26.8% PA drain efficiency. Measurement with 16-QAM signal exhibits the PA's flexibility on optimizing efficiency and linearity.