Drain Edge Research Articles

(Invited) Hot Carrier Phenomena in Oxide Thin-Film Transistors

Oxide thin-film transistors (TFTs) using amorphous oxide semiconductors such as a-InGaZnO4 (a-IGZO) are attracting attention for realizing next generation displays as well as for flexible mobile devices. From a point of practical use, it is important to achieve stable electrical characteristics in oxide TFTs. Thus various reports have been made on instability of oxide TFTs’ characteristics, such as threshold voltage shift and a light deterioration phenomenon caused by application of bias voltage or light illumination.1-3) Hot carrier effects, however, induced by high drain voltage in oxide TFTs have been still unclear.Hot carrier effects are well-known phenomena in low temperature polycrystalline Si TFTs, and photon emission has been observed under high drain voltage.4) In recent years, we also have observed photon emission under high drain voltage for etch stop layer (ESL)-type oxide TFTs with a source/drain (S/D) that overlapped less than 1 µm on ESL.5) In this paper, we discuss the hot carrier effects depends on structures of oxide TFTs.We fabricated back channel etching (BCE)-type, top gate (TG)-type and ESL-type5) TFTs using oxide semiconductor material as active layers as shown in Fig. 1(a), (c) and (e), respectively. For BCE-type TFTs, a gate, a gate insulator, a-IGZO, S/D and a passivation were formed on a glass substrate in that order. For TG-type TFTs, low resistance regions in amorphous oxide semiconductor layer, which has higher mobility than a-IGZO, were self-aligned to the gate. For the ESL-type TFTs, an overlap length of the S/D on the ESL was 3 µm. Other fabrication process were described in previous report.5-6) As shown in Fig. 1(b), for the BCE-type TFT with channel width (W) /channel length (L) =15 µm/8 µm under Vds=25 V and Vgs=10 V, photon emission was observed at the drain edge opposite to the source. Two positions where most photon was irradiated correspond to those where the drain slightly extends to the source. As shown in Fig. 1(d), for the TG-type TFT with W/L = 10 µm/10 µm under Vds=40 V and Vgs=18 V, photon emission was observed at the gate edge opposite to the drain and at the drain edge opposite to the gate. For both these two regions, positions where most photon was irradiated correspond to the edge of active layer, which is often pointed out as one of the causes of instability of TFT characteristics.6) Although drain current (Ids) increased at higher Vgs than Fig. 1(b) and (d), photon counts decreased. From these results, we consider the observed photon emission were induced by hot carrier in the oxide semiconductor layers and photon emission images show regions which may affect instability of TFT characteristics.On the other hands, for the ESL-type TFT with channel width (W) /channel length (L) =5 µm/14 µm, photon emission was not observed even under drain voltage (Vds) =40 V and gate voltage (Vgs) =12 V as shown in Fig. 1(e). However, we experimentally observed that when the overlap length of the drain on the ESL decreases from 3 µm to 0 µm, photon emission was observed. Furthermore, TCAD simulation showed that the large electric field of 3.5×105 V/cm appears locally at the drain edge for the overlap length=0 μm while that relaxed to less than 2.2×105 V/cm for the overlap length>1 μm. These results suggest that existence of the drain/ESL overlap region can weaken the electric filed at the drain edge, and as a result we do not see photon emission in the ESL-type TFT with the overlap length=3 µm.In summary, we evaluated hot carrier effect for the BCE-, the TG-type and the ESL-type oxide TFTs with photon emission analysis. Photon emission was observed for the BCE- and the TG-type TFT while it was not observed for the ESL-type TFT with the overlap length of the drain on the ESL=3 µm. We consider one of reasons of these results would be difference in the structure near the drain of each TFT. In the PRiME 2020 meeting, we would like to discuss these phenomenon in detail using experiment and TCAD simulation.References1) K. Takechi et al., Jpn. J. Appl. Phys., 48, 010203 (2009).2) J. Tanaka et al., ECS Journal of Solid State Science and Technology, 4 (7) Q61 (2015).3) Y. Uraoka et al., Jpn. J. Appl. Phys., 58, 090502 (2019).4) Y. Uraoka et al., IEEE Trans. Electron Devices, 51, 28 (2004).5) T. Takahashi et al., Appl. Phys. Express, 12, 094007 (2019).6) Y. Kuwahara et al., IEEE Electron Device Lett., 40, 8 (2019). Figure 1

Channel-length dependence of the generation of interface states and oxide-trapped charges on drain avalanche hot carrier degradation of HfSiON/SiO2 p-channel MOSFETs with strained Si/SiGe channel

This paper evaluates how channel length L affects the drain avalanche hot carrier degradation (DAHC) degradation mechanism of HfSiON/SiO2 pMOSFETs that have strained Si/SiGe channel. DAHC degradation occurred as L was to reduced < 70 nm, and the amount of degradation increased as L decreased. In the early stage of stress, DAHC degradation increased positively due to generation of negative oxide charges –Qox, but gradually-generated interface states Nit neutralize –Qox, so a transition point occurs and eventually DAHC increases negatively after sufficient stress time ts. The distribution of DAHC degradation was also analyzed after ts = 4000, 40000 s. The effects of additional generation of –Qox and Nit on DAHC degradation contribute more near the drain edge than to the center region, and increase as L decreases. Therefore, further research on the DAHC degradation mechanism should be conducted to predict the reliability of HfSiON/SiO2 pMOSFETs with mechanical strain engineering.

Thermal Management of GaN-on-Si High Electron Mobility Transistor by Copper Filled Micro-Trench Structure

Self-heating effect is a major limitation in achieving the full performance potential of high power GaN power devices. In this work, we reported a micro-trench structure fabricated on the silicon substrate of an AlGaN/GaN high electron mobility transistor (HEMT) via deep reactive ion etching, which was subsequently filled with high thermal conductive material, copper using the electroplating process. From the current-voltage characteristics, the saturation drain current was improved by approximately 17% with the copper filled micro-trench structure due to efficient heat dissipation. The IDS difference between the pulse and DC bias measurement was about 21% at high bias VDS due to the self-heating effect. In contrast, the difference was reduced to approximately 8% for the devices with the implementation of the proposed structure. Using Micro-Raman thermometry, we showed that temperature near the drain edge of the channel can be lowered by approximately ~22 °C in a HEMT operating at ~10.6 Wmm−1 after the implementation of the trench structure. An effective method for the improvement of thermal management to enhance the performance of GaN-on-Silicon HEMTs was demonstrated.

Hot carrier effects in InGaZnO thin-film transistor

Photon emission and the electrical characteristics of a InGaZnO (IGZO) thin-film transistor (TFT) were evaluated to clarify the existence of hot carriers and their effects. The photon emission was observed from the drain edge of the IGZO-TFT and the capacitance–voltage characteristics indicated that a potential barrier was formed at the drain region when the device is driven by high drain voltage of 30 V. Based on these results, the photon emission phenomenon from the IGZO-TFT was induced by hot carriers that should be considered as a significant degradation mode for a high-performance oxide semiconductor device.

Analysis of Breakdown Voltages in AlGaN/GaN HEMTs With Low-${k}$ /High-${k}$ Double Passivation Layers

2-D analysis of off-state drain current–drain voltage characteristics in AlGaN/GaN HEMTs is performed; where three cases with single passivation layers (SiN or high- ${k}$ dielectric) and double passivation layers (first layer: SiN, second layer: high- ${k}$ dielectric) are compared. The passivation layer’s thicknesses and relative permittivity of high- ${k}$ dielectric are varied as parameters. It is shown that in the case of double passivation layers, the breakdown voltage is enhanced significantly compared to the case of the SiN single passivation layer when the second high- ${k}$ layer becomes thick. This occurs because the electric field at the drain edge of the gate is reduced. However, in the case of a relatively thin second high- ${k}$ layer, the breakdown voltage can be lowered remarkably compared to the case with a high- ${k}$ single passivation layer even if the first SiN layer is rather thin. Also, when the first SiN layer is thick ( ${\sim } 0.1~{\mu }\text{m}$ ), the improvement of the breakdown voltage by increasing the thickness of the second layer is rather limited. However, it is also shown that in the case of double passivation layers, the breakdown voltage becomes close to the case of the high- ${k}$ single passivation layer when the relative permittivity of the second passivation layer becomes high and the SiN layer is relatively thin.

Degradation Model of a-IGZO TFT due to High Drain Bias Stress

In this paper, the TCAD degradation model of IGZO using spatial distribution (X, Y) of physical parameters is proposed for the first time and is confirmed according to various channel length, active thickness, and bias stress conditions that agree with actual measurements. The asymmetric degradation phenomenon according to the source/drain sweep direction occurs when high VDS stress (> 40 V) is applied to a-IGZO TFT due to the local strong electric field in the drain edge region in the active channel. In the double side gate (DSG) structure, the degree of degradation varies according to VTG, which is influenced by the concentration of electrons induced in the channel. Oxygen vacancy in the presence of 2+ ionized states (VO2+) in IGZO is stable. However, when band bending is severe, the electrons are captured, and the structural transition occurs as a neutral VO in the meta-stable state. This process is assumed to be a mechanism of IGZO degradation at high drain bias stress, and the electric field (>0.5M V/cm) and electron concentration (>1 × 1010 cm−3) in the channel are considered as the main factors of degradation and are modeled using the mapping function provided by Silvaco.

Evolution of field dependent carrier trapping during off-state degradation for GaN based metal oxide semiconductor high electron mobility transistors

We have shown that the off-state degradation in GaN based metal-oxide-semiconductor high electron mobility transistors has three field dependent regimes. We have considered Al2O3 and AlOxNy as the gate dielectrics. The degradation is dominated by electron trapping near the drain edge at relatively low electric field; hole trapping followed by structural defects tends to dominate at high electric field. The structural defects may potentially be caused by an inverse piezoelectric effect when the AlGaN/GaN interface may relax partially. The hole trapping, in particular, at moderate to high electric field can lead to an anomalous trend. The off-state drain current bears the signature of the degradation. The transistor performance is found to deteriorate for all the cases independent of the degradation mechanism. The trapping contribution toward the degradation is partially recoverable; however, the structural damage is found to be permanent. It is also observed that both the gate dielectrics qualitatively suffer from the same degradation mechanism with oxynitride high electron mobility transistors showing higher resilience than their oxide counterpart.

Enhancement of Breakdown Voltage in AlGaN/GaN HEMTs: Field Plate Plus High-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${k}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Passivation Layer and High Acceptor Density in Buffer Layer

We make a 2-D analysis of breakdown characteristics of field-plate AlGaN/GaN HEMTs with a high- ${k}$ passivation layer, and the results are compared with those having a normal SiN passivation layer. As a result, it is found that the breakdown voltage is enhanced particularly in the cases with relatively short field plates because the reduction in the electric field at the drain edge of gate effectively improves the breakdown voltage in the case with the high- ${k}$ passivation layer. In the case with the moderate-length field plate, the enhancement of breakdown voltage due to the high- ${k}$ passivation layer occurs because the electric field profiles between the field-plate edge and the drain become more uniform. It is also studied how the breakdown voltage depends on a deep-acceptor density in the Fe-doped semi-insulating buffer layer when a high- ${k}$ passivation layer is used. It is shown that the breakdown voltage increases with increasing the relative permittivity of the passivation layer $\varepsilon _{\text{r}}$ and with increasing the deep-acceptor density NDA. When $\varepsilon _{\text{r}} = 60$ and $N_{\mathrm {DA}} = 2$ – $3 \times 10^{17}$ cm−3 at the gate length of $0.3~\mu \text{m}$ , the breakdown voltage becomes about 500 V at a gate-to-drain distance of $1.5~\mu \text{m}$ , which corresponds to an average electric field of about 3.3 MV/cm between the gate and the drain.

(Invited) Design and Reliability of GaN Power HEMT Technology

Gallium nitride (GaN) based high electron mobility transistors (HEMTs) are extensively being considered for power and RF applications by virtue of their unique properties. AlGaN/GaN HEMTs are depletion mode devices due to presence of high density 2DEG at the interface. However, enhancement mode devices prove beneficial for simpler and reliable power systems. F implant, p-GaN gate and AlGaN recess are some of the widely accepted processes to achieve the same. In spite of extensive research already being carried out in the domain, the search for a reliable technique for e-mode GaN with superior performance metric is still continued. A novel technique incorporating a p-type metal oxide in conjunction with partial recess of AlGaN has been established to demonstrate a high performing e-mode GaN/AlGaN HEMT. The p-type metal oxide helped in positive shift of the VTH which allowed the device to be e-mode even with partial recessing. This helped circumventing the challenges introduced by plasma damage in recess-based e-mode GaN HEMTs. Besides HEMTs, GaN based Schottky diodes have started gaining prominence for power applications. Schottky diodes with high ON current (1A/mm), 0.5 V cut in voltage and reduced reverse leakage were demonstrated by carrying out surface treatment post AlGaN recess. The high temperature anneals, and acid treatments helped reduce the surface damage induced due to plasma. Technology CAD (TCAD) based design approach goes a long way in designing improved and reliable devices. Hence a consistent and reliable TCAD strategy that can be employed for HEMT analysis and design of high performance HEMTs is the need of the hour. The presence of unique polarization effects combined with traps, hot electrons and self-heating make reproducing accurate device behavior for HEMTs a challenging task. A well-defined Technology CAD strategy is developed for the first time for GaN HEMT, incorporating all the physical aspects pertaining to HEMT. The simulation setup was well calibrated with the experimental data. TCAD based Co-Design guidelines were proposed, which can be effectively utilized to optimize the design parameters for maximum RF and breakdown performance. Further novel designs- RESURF, Superjunction and Stepgate were proposed having high breakdown voltages. Comprehensive study was done to study the physical effect of surface traps and buffer traps on the breakdown performance. GaN based HEMTs despite of its attractive performance/cost ratio, suffers from poor reliability which limits its penetration in the ever-growing power device market. Therefore, reliability of AlGaN/GaN HEMT is now a topic of intense research. The present understanding of underlying degradation physics needs to be improved further. Many aspects like ability of GaN HEMT to handle high power under extreme conditions and related SOA concerns are yet to be investigated. Characterization of HEMT can be done under dc and pulse stress. In pulse characterization, one can emulate real stress conditions present in power electronic circuits. On the fly dc I-V and C-V gives information about the device degradation whereas sub-bandgap UV is used to capture trapping effects. Besides, on the fly Raman captures evolution of piezoelectric/ thermal stress in HEMT. It has been observed that carrier trapping has significant impact on SOA of GaN HEMTs. High trap density causes electric field shift and peaking towards drain edge. The field enhancement at drain accelerates impact ionization and carrier injection into buffer leading to early filament formation. Non-uniform trapping along width triggers avalanche instability. The SOA boundary is found to deteriorate in OFF-state, due to compressive stress at drain-gate edge. ON-state SOA is also limited by tensile stress in the gate-to-drain region. The electric field profile in channel and buffer can be tuned by controlling the recess depth, which directly affects device degradation and SOA. Figure 1

Trapping Effects in Si -Doped -Ga2O3 MESFETs on an Fe-Doped -Ga2O3 Substrate

Threshold voltage instability was observed on $\beta $ -Ga2O3 transistors using double-pulsed current–voltage and constant drain current deep level transient spectroscopy (DLTS) measurements. A total instability of 0.78 V was attributed to two distinct trap levels, at ${E}_{C}$ -0.70 and ${E}_{C}$ -0.77 eV, which need to be mitigated for future applications. The traps are likely located near the gate–drain edge and below the delta-doped layer, which is determined through the DLTS technique and an understanding of the fill and empty biasing conditions. The trap modulation was consistent with a gate leakage-based trap filling mechanism, which was demonstrated. It is likely that Fe is playing a role in the observed dispersion due to the close proximity of the Fe substrate.

Towards InGaAs MS-DRAM Memory Cells

The need of a low-power, fast and low-cost CMOS compatible embedded DRAM cell is rising incessantly with the upcoming Internet of Things (IoT) era [1]. Capacitor-less DRAM cells [2, 3] have emerged as a promising solution since they do not require dedicated fabrication steps to deal with the storage node. Among this breeze of cells, the MSDRAM [4] can be highlighted due to the simpler manufacturing process. The MSDRAM (Meta-Stable-Dip RAM) memory operation is based on inter-gate coupling [5] and non-equilibrium state [6]. The back gate (ground-plane) is biased positively to induce a virtual n-type back-channel while the front-gate voltage is negative to retain any available hole in the body. By modulating the hole population at the front-channel, the vertical top-gate induced electric field is screened (or not) so that the back electron-channel is maintained (or depleted). Depending upon the back-channel depletion degree different conductance values are achieved defining the logic ‘1’ and ‘0’ memory states. State programming is carried out by injecting holes by band-to-band tunneling at the drain edge (W1) or evacuating holes by top-gate capacitive coupling (W0) In this work, a III-V InGaAs MSDRAM cell is built and its memory operation is demonstrated by TCAD numerical simulations in Synopsys [7, 8]. The detailed structure and the doping are shown in Fig.1. The basic memory operation is depicted in Fig. 2a for a W0-R-W1-R-W0-R sequence with W1/0 being the ‘1’/’0’ state programming and R the reading. The current after any W0 operation remains much lower than after W1. Figure 2b represents the body electron and hole densities after the first W0 and W1, respectively. Following W0, the hole density is limited underneath the top dielectric allowing a strong vertical field that depletes the back-channel from electrons leading to a drastic drop in the conductance and thus in the drain current. On the contrary, after generating holes by band-to-band tunneling during W1, the electron back-channel is reinforced enabling a larger current level while reading afterward. In conclusion, preliminary TCAD results demonstrate the feasibility of implementing the MSDRAM concept on III-V materials. REMINDER project (No 687931) is thanked for support. Figure 1

An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET

In this paper, we have developed a methodology of a lateral profiling technique of the channel local temperature in 14 nm FinFET, incurred by the self-heating effect (SHE). As SHE happens, the thermal source generated near the drain will dissipate toward the source side. Since the interaction between RTN trap and channel carriers is very sensitive to the temperature, the channel local temperature can be extracted through this interaction process between random-telegraph-noise (RTN) trap and carriers, and the position of the channel local temperature can be obtained from the RTN trap position. The results show that the highest temperature happens at the drain edge during SHE and pFinFET exhibits a much higher temperature than that of nFinFET. Furthermore, the distribution of channel local temperature can be described by the Fourier’s law of thermal conduction. Averaged channel temperature can be used to extract the thermal resistance, $R_{\mathrm{ th}}$ , which increases rapidly as the channel length is scaled down to 20 nm, further degrading the SHE, in terms of a significant short channel effect. We also found that the incremental channel resistance is proportional to the incremental channel local temperature, whose slope indicates the degree of SHE, and the slope of pFinFET is larger than that of nFinFET. Finally, SHE will cause 10% and 14% degradation of $I_{\mathrm{ d}} V_{\mathrm{ ds}}$ for n- and pFinFET respectively. This can be reasonably explained by the decay of saturation velocity in high temperature. The results obtained based on this methodology will help us on the understanding of the SHE impact on a nano-scaled FinFET device.

Reliability Characteristics and Mechanisms of HRL’s T3 GaN Technology

HRL’s T3 GaN MMIC technology is evaluated using dc reliability experiments, including a voltage step-stress test, a temperature step-stress test, and a 3-temperature life test. The drain voltage step-stress test revealed three distinct regions of operation through gate leakage characteristic changes: burn-in stabilization up to 5 V, followed by stable operation up to 20 V, then voltage-dependent degradation up to catastrophic failure around 30 V. As a result, a de-rated recommended safe-operating limit of Vds = 12 V was established. The temperature step-stress test resulted in clear Arrhenius temperature-dependent degradation of the device on-resistance above 250 °C. Similarly, a recommended safe-operating limit of 150 °C was established for the technology. Finally, the 3-temperature life test resulted in clear temperature group separation and an activation energy of 2.52 eV, with a mean time-to-failure of 4 million hours at 150 °C with only a +0.2 ohm.mm increase in device on-resistance. Physical failure analysis of degraded parts showed the mechanism was a defect formation in the epitaxial barrier layer at the drain edge of the gate. Finite-element electrical simulations duplicated this degradation mechanism by modeling the defect as a void, which depleted the 2DEG and therefore increased device on-resistance.

(Invited) Electric Field Control in AlGaN/GaN Hemts Operating in the Kilovolt Regime

AlGaN/GaN High Electron Mobility Transistors (HEMTs) are very promising devices for the next generation of high-voltage power electronics. Their ability to achieve a low on-state resistance due to the high electron mobility in the 2DEG conduction channel formed by the GaN quantum well created at the AlGaN/GaN interface, as well as the fact that they have effective breakdown fields on the order of 106 V/cm, due to the wide bandgap of GaN (Eg = 3.4 eV), make them promising devices to operate in the kilovolt (kV) regime. Additionally, AlGaN/GaN HEMTs are majority-carrier devices which allow enhanced switching speeds at high voltages, conditions of high power dissipation, and high temperature conditions. Although the wide bandgaps of GaN and AlGaN in theory can enable the high-frequency switching capability of such unipolar field effect transistors to be extended to the kilovolt regime, the measured Figure of Merit (FOM, i.e., the breakdown voltage squared divided by the area-normalized on-resistance) for state-of-the-art commercial HEMTs continues to be well below values predicted by the FOM expected for an ideal device exhibiting a uniform electric field profile between the gate and drain. In fact, the difficulty of scaling the breakdown voltage of AlGaN/GaN HEMTs to kV levels is largely due to large electric field spikes in the active region that cause premature breakdown. In today’s devices, much of the channel voltage drop in the off-state occurs near the drain-side edge of the gate electrode. This voltage drop produces an electric field which can cause excessive gate leakage currents, and breakdown occurs at a much lower voltage than predicted by assuming an ideal, uniform electric field profile extending from the gate to the drain edge. While use of appropriate device passivation and encapsulation increases breakdown voltage by eliminating surface flashover, the fundamental problem of voltage scalability due to the non-uniform field distribution is evidenced by studies which show that breakdown voltage will not continuously increase as a function of increasing gate-to-drain spacing. This is true even if existing approaches such as source- and gate-connected field plates are employed; these mitigate the problem, but still result in a field distribution that is far from optimum. Consequently, other schemes for mitigating high electric fields need to be considered. Hence, in this talk we present results for AlGaN/GaN HEMT simulations that compare the effectiveness of various field plate implementation schemes in mitigating electric field spikes in the GaN channel so as to provide a more uniform electric field distribution. From these studies, the value of utilizing a distributed impedance “field-cage” structure is made apparent, and we also discuss the implementation of continuous “resistive field plate” (RFP) structures for electric field management. In the field cage scheme, a resistive voltage divider network fabricated on the device surface provides electric field control throughout the active region. The electric field in this region is determined to become progressively more uniform as the source-drain voltage is increased, indicating that the field cage scheme is promising for achieving breakdown voltage scalability. We also discuss the optimization of parasitic capacitances in the field cage in order to improve electric field control for AC ramps as high as dV/dt = 100V/ns. The RFP scheme, on the other hand, relies on making use of a continuous resistive material deposited between the gate and the drain in order to achieve a linear drop in electric potential and hence a constant field. From a processing standpoint, implementing RFP structures is perhaps less challenging that that of the field cages, as the fabrication of discrete components on the passivation layer would not be needed. However, finding a material with the appropriate resistivity that is easily integrated into the HEMT process may be a challenge. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.

Electroluminescence Microscopy of Cross-Sectioned AlGaN/GaN High-Electron Mobility Transistors

We report an electroluminescence (EL) microscopy study of operating cross-sectioned AlGaN/GaN high-electron mobility transistors. By examining devices in a cross-sectional view, the distribution and intensity of photons emitted from underneath the optically opaque metal of the gate and drain structures can be studied. The location and the shape of EL bright spots were quantitatively compared with simulated device behavior, revealing a strong correlation between the measured EL intensity and the expected distribution of hot electrons in the channel. Under constant low-power conditions, the bulk of the EL signal migrates from the drain edge of the gate field plate to the drain edge of the source-connected field plate (SCFP) as the drain bias is increased. Hot electrons have been cited as a dominant contributor to device degradation for some devices, so quantifying their location and bias dependence is critical to understanding how this degradation rate might scale with bias and device design. In addition, devices both with and without an SCFP were imaged to quantitatively investigate the influence of the field plate on the EL signal. Finally, a measurement of the spectra of EL signals is used to estimate the temperature of hot electrons in the device.

Analysis of breakdown characteristics in source field‐plate AlGaN/GaN HEMTs

AbstractTwo‐dimensional analysis of off‐state breakdown characteristics of source field‐plate AlGaN/GaN HEMTs is performed by considering a deep donor and a deep acceptor in a buffer layer. It is shown that the introduction of field plate is effective in improving the breakdown voltage, but it can decrease with the field‐plate length, and hence its optimum length should exist. It is also shown that the breakdown voltage of the source field‐plate structure is a little lower than that of the gate field‐plate structure when the field‐plate length is short, because the electric field at the drain edge of the gate becomes higher. (© 2015 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Trapping Effects at the Drain Edge in 600 V GaN-on-Si HEMTs

In this paper, we investigate the influence of the drain electrode on the dynamic switching behavior of AlGaN/GaN high-electron-mobility transistors on Si substrate. By adding a field plate to the drain electrode, a dramatic increase in the dynamic ON-resistance dynR $_{\mathrm{\scriptscriptstyle ON}}$ was identified. The dispersion effect is correlated with the high electric field below the drain field plate (DFP), the onset of which is caused by the full electron depletion from both the channel and the GaN cap layer. We show that the electron distribution is modified by the passivation method, backside bias, or surface charges and, hence, shifts the onset voltage of the trapping effect. Trapped electrons underneath the DFP are thought to be responsible for the measured rise of the dynR $_{\mathrm{\scriptscriptstyle ON}}$ . With the introduction of an extended ohmic drain contact, the influence of a metallization overhang at the drain edge can be suppressed. The detrapping energies associated with the surface defects were determined to 0.2, 0.3, and 0.7 eV, respectively. Simulations and measurements indicate that charges inside the passivation below the DFP worsen the switching behavior.

Impact of a drain field plate on the breakdown characteristics of AlInN/GaN MOSHEMT

In this paper, a novel AlInN/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT) employing the drain field plate technique is proposed and the effect of a drain field plate on the breakdown voltage (BV) is investigated. A reduction of the peak electric field is required to achieve AlInN/GaN MOSHEMTs with a high BV. The proposed AlInN/GaN MOSHEMT with both gate and drain field plates simultaneously reduces the electric field concentration at the gate and the drain edge by decreasing the potential gradient along the channel for the 2 dimensional electron gas (2DEG). The reduction in the peak electric field at the drain edge of the proposed device leads to a 57% increase in BV compared with the BV for an AlInN/GaN MOSHEMT with a gate field plate only. A significantly higher BV can be achieved by optimizing the gate-to-drain distance (Lgd), the length of the drain field plate (Ldfp) and the thickness of the SiN passivation layer thickness (TSiN). A detailed breakdown analysis of the device was carried out using Silvaco Technology Computer Aided Design (TCAD). The detailed numerical simulations were done by using the non-local energy balance (EB) transport model, which was calibrated with the previously published experimental results. The results showed a great potential for applications of the drain-field-plated AlInN/GaN MOSHEMT to deliver high currents and high powers in microwave technologies.

Effects of buffer leakage current on breakdown characteristics in AlGaN/GaN HEMTs with a high-k passivation layer

A two-dimensional analysis of off-state breakdown characteristics in AlGaN/GaN HEMTs is performed by considering a deep donor and a deep acceptor in a buffer layer, with the relative permittivity of passivation layer εr as a parameter. The analysis is made with and without impact ionization of carriers to study how the buffer leakage current affects the breakdown performance. It is shown that when εr is low, the breakdown voltage is determined by the impact ionization of carriers, and when εr becomes high, it is determined by the buffer leakage current. This buffer leakage current decreases as εr increases because the electric field at the drain edge of the gate is weakened, and hence the breakdown voltage increases as εr increases. It is also shown that when the gate voltage is more negative, the breakdown voltage in the high εr region becomes higher because the buffer leakage current becomes smaller.

The vacancy defect in graphene nano-ribbon field-effect transistor in the presence of an external perpendicular magnetic field

In this paper, we investigate effect of vacancy defect on graphene nano-ribbon field effect transistor (GNR-FET) in the presence of an external perpendicular magnetic field. Our simulation is based on Non-Equilibrium Green's Function (NEGF). The nearest neighbor tight-binding model based on pz orbital construct the device Hamiltonian. Also we calculate magnetoresistance (MR) for different position vacancies in presence B-field. We find an external B-field causes the conductance of the GNR increases, giving rise to the MR effect. The simulation results indicate in the presence of a small B-field the current is degraded because the vacancy defect act as scattering and the conductance decreases due to defects compared with the perfect nanoribbons and the MR is reduced but in the hall quantum regime the probability of being scattered by the vacancy reduced due to the electrons are more localized at edge states and this phenomena to enhance the MR ratio of the device. The results indicate that the defect near drain and near edge has the largest MR ratio in the presence of a small B-Field and in the hall quantum the defect near source has the largest MR ratio.