Drain Edge Research Articles

Novel double deck gate field plate structure on a normally-off AlGaN/GaN HEMT- An extensive analysis

A novel double deck gate field plate structure on a normally-off AlGaN/GaN HEMT is proposed and compared with the conventional no field plate structure. Several passivation materials with relative permittivity (εr) ranging from 3.9 to 22 is taken into consideration to study the breakdown and DC characteristics. The implementation of field plate along with a higher εr material helps in improving breakdown voltage (VBr) as they both decrease the electric field at the gate's drain edge. Aiming device optimization several field plate configurations are studied including tri field plate structure, dual field plate structures and single gate FP structure. Extensive analysis in these structures are done with different lengths of the field plates and distance between source and drain. Distance between source and drain (LSD) is varied from 8.4 to 13.4 μm, source FP lengths (LS_FP) varies from 1 to 7 μm, gate FP lengths (LG_FP) varies from 0.9 to 2.3 μm and drain FP lengths (LD_FP) varies from 0.2 to 4.9 μm. In all scenarios with varying LSD, VBr rises with increasing LSD. For source, gate and drain FP lengths variation, VBr decreases as it gets longer because the electric field becomes very high. As the distance between the FP edge and the drain becomes narrower with increase in FP lengths, the breakdown occurs at lower voltage. At LSD 13.4 μm, this novel double deck gate FP structure with conventional drain field plate structure gives highest VBr of 1660 V and a small Ron of 2.39 Ω mm as compared to other structures. It also outperforms the other three structures in FT (9.84 GHz) at this particular LSD. Analysis of the simulated structures shows that the union of gate-drain field plate boosts the VBr while decreasing the Ron, resulting in improved electrical performance and a wider application range.

Study on the single-event burnout mechanism of p-GaN gate AlGaN/GaN HEMTs

In this work, the single-event burnout (SEB) mechanism of p-GaN gate AlGaN/GaN HEMTs has been studied systematically. The irradiation experiment was carried out based on Ta ions with high linear energy transfer of 75.4 MeV/(mg/cm2), a standard criterion for commercial space applications. It is clearly observed that both the drain current and gate current increase during the irradiation. With the increasing drain bias, the device burns out eventually. Technology computer-aided design simulation was used to explore the possible burnout mechanism. The local high electric field peak induced by the electron and hole redistribution was proposed to explain the permanent damage. When heavy ions impact the device, electron–hole pairs are formed. With the aid of a horizontal electric field across the channel, electrons and holes move toward the drain and gate, respectively. The accumulation of electrons and holes around the drain edge and gate edge induces the local high electric field, which is even higher than the intrinsic breakdown electric field of GaN and AlGaN. The scanning electron microscope results verified the proposed SEB mechanism. This research offers significant theoretical and experimental insights for evaluating the reliability of GaN power devices against high-energy single-event burnout in aerospace applications.

A dielectrically modulated vertical TFET-based biosensor considering irregular probe placement and steric hindrance issues

This manuscript presents a comparative biosensing analysis of a dielectrically modulated dual-drain vertical TFET (DD-VTFET) by considering three distinct device arrangements based on the cavity position. DD-VTFETs with single cavity at the source and drain edge are called SC-DD-VTFET and DC-DD-VTFET, respectively, while for SDC-DD-VTFET, dual cavities are created at both the source and drain edge. Asymmetry in cavity position results in different electrostatics for each biosensor, leading to variation in their sensing performance. The on-current sensitivity is found to be lower for the DC-DD-VTFET due to the absence of cavity near the channel-source interface, while the SC-DD-VTFET shows poor performance in terms of ambipolar current sensitivity compared to the SDC-DD-VTFET. Moreover, the study includes the consideration of neutral and charged biomolecules (both positive and negative) with varying dielectric constants of 5, 7, 10 and 12. The sensitivity of partially filled nanogaps with fill-factor (FF) of 42% and 60%, influenced by steric hindrance, are also compared for all three DD-VTFET based biosensors which includes different step profiles of biomolecules, such as concave, convex, increasing, and decreasing. To consider the non-ideal state of the DD-VTFET based biosensors, the effect of irregular placement of the probe within the nano-cavity on different sensitivity parameters for a particular k-value of biomolecules is also analysed using TCAD simulator. Furthermore, the performance of the DD-VTFET based biosensor is quantitatively benchmarked against previously published works available in the literature. For a fully filled cavity with neutral biomolecules having dielectric constant of 12, SDC-DD-VTFET based label-free biosensor provides ON-current and current-switching ratio sensitivities approximately in the order of 105, while the ambipolar current sensitivity of 2.1×103 is observed which makes the sensor equally suitable for sensing the biomolecules even at negative gate bias.

Reliability of enhancement-mode p-GaN gate GaN HEMT with multiple field plates

In this paper, we fabricate enhancement-mode p-GaN gate GaN HEMTs with multiple field plates (MFPs) and analyze the reliability of the devices by means of simulation and experiment. Simulations of the electric-field distribution indicate that the MFPs effectively weaken the electric field peak near the gate to below the theoretical breakdown value and smooth the electric field between the gate edge and drain-side field plate edge. The simulated electric field peak leading to the breakdown of the device with MFPs at high drain voltage is located at the drain edge, which is validated by experimental results. The GaN HEMTs with MFPs exhibit excellent long-term reliability under high temperature and drain voltage, while deviations from threshold voltage and on-resistance were observed in the device subjected to drain stress. We attribute these deviations to electron accumulation and high field-assisted detrapping processes in the p-GaN layer. This investigation provides new insight into the mechanism of variations in threshold voltage and on-resistance under off-state drain stress.

Investigation of dynamic ron stability and hot electrons reliability in normally-off AlGaN/GaN power HEMTs

The current collapse and hot electron effect of 100 V normally-off GaN power HEMTs are investigated. The 100 V GaN-on-Si power HEMTs are fabricated on an industrial 200 mm Si CMOS compatible technology platform. The double pulse test (DPT) and the dynamic high temperature operating life (DHTOL) test are implemented to verify the dynamic on-resistance (dynamic Ron) stability. Wafer level hot electron reliability test is performed to investigate the effect of high electric field and high current on GaN power HEMT. It is proved that the dynamic Ron stability of 100 V GaN power HEMT is qualified (Ron/Rini, static < 1.2) when the drain-source off-state voltage (Vdsoff) is less than 80 V. It is shown that the dynamic Ron degradation of GaN device is recoverable by means of annealing. Hot electrons reliability is dominated by the high electric field at drain edge and the high current which is source injected electrons flowing to the drain. It is demonstrated that the Vth drift and Ron degradation are extraordinary serious under semi on-state stress condition with Vdsoff = 60 V.

(Invited) Switching Characteristics of GaN Power Transistors

A shorter switching time and smaller conduction and switching losses are the key advantages of GaN power devices over Si technology. Further improvements of GaN HEMT technology will require new design approaches including SiC and even, possibly, diamond substrates, gate and drain edge engineering (beyond just using field plates) for optimizing the voltage distribution in the drain-to-gate spacing to using perforated channel design and a low conducting passivation for smoothing or even eliminating the sharp maximum of the electric field in the vicinity of the gate and field plate edges on switching time.

Simulation study on single-event burnout in field-plated Ga2O3 MOSFETs

This paper presents the 2-D numerical simulation results of the heavy-ion induced single-event burnout (SEB) and single event gate rupture (SEGR) in the depletion-mode gallium-oxide (Ga2O3) field-plated metal-oxide-semiconductor field-effect transistors (FP-MOSFETs). The employed simulation physics models and material parameters were validated by the basic electrical characteristics in experiments. The SEB sensitive region was proven to be from the gate edge to the drain edge of the structure. The SEB failure could result from the large number of mobile holes that diffused into the strong electric field to form a very large joule heat power to induce thermal failure. Meanwhile, the SEGR sensitive region overlapped with that of the SEB. The accumulated at the gate channel interface could produce a high-density hole pool that formed a large positive potential to induce an SEGR. Based on the simulations, a catastrophic SEB was triggered at a drain voltage of around 350 V, which was 46.4 % of breakdown voltage. Besides, a severe leakage current degradation could be estimated at about 175 V. However, for the SEGR performance, an SEGR could be triggered even at 0 V. Finally, the influences of the field plate extension length on SEB and SEGR were investigated that the SEB sensitive region and maximum electric field during SEGR could be both improved.

Effect of Acceptor Traps in GaN Buffer Layer on Breakdown Performance of AlGaN/GaN HEMTs.

In this paper, Silvaco TCAD software is used to simulate the buffer traps in AlGaN/GaN high electron mobility transistors (HEMTs), and its effects on the breakdown performance and key parameters of the devices are investigated by changing the position and concentration of the acceptor traps in the buffer layer. The results show that with the increase of trap concentration, the traps capture electrons and reduce the off-state leakage current, which can improve breakdown voltage of the devices. At the same time, as the trap concentration increases, the ionized traps make a high additional electric field near the drain edge, leading to the decrease of breakdown voltage. With the combined two effects above, the breakdown voltage almost ultimately saturates. When the source-to-gate (Access-S) region in the GaN buffer layer is doped alone, the minimum and most linear leakage current for the same trap concentrations are obtained, and the additional electric field has a relatively small effect on the electric field peak near the drain as the ionized traps are furthest from drain. All these factors make the breakdown voltage increase more controllably with the Access-S region doping, and it is a more potential way to improve the breakdown performance.

Comparison of lateral spillway and morning glory spillway performance in flood control

With the emergence of climate change and the increasing human intervention in the global climate, floods have affected different parts of the world. In practice, floods are the most terrible natural disaster in the world, both in terms of casualties and financial losses. To reduce the adverse effects of this phenomenon, it is necessary to use structural and non-structural methods of flood risk management. One of the structural methods of flood control is to allocate a certain part of reservoir dams to flood control. In order to safely exit the flood from the dam reservoir, the spillway structure should be used. One of the important issues in designing a spillway structure is reducing its construction costs. In order to safely exit the flood with a specified return period from the dam reservoir, as the length of the spillway decreases, the height of the water blade on the spillway increases. In other words, decreasing the spillway length increases the height of the dam and its construction and design costs. In this study, the design and comparison of the performance of two glory spillways and lateral spillways have been considered. The results showed that for a given length for the drain edge of both types of spillways, the height of the water blade on the glory spillway is always higher than the lateral spillway. For example, when a 10,000-year-old flood occurs, it is about 8 m.

Abnormal Two-Stage Degradation on P-Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor Under Hot Carrier Conditions

In this study, an abnormal two-stage degradation of low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) on a polyimide flexible substrate after hot carrier stress was investigated. The degradation mechanism was divided into two stages. In the first stage, the increases in capacitance in the off region and transconductance are caused by impact ionization induced electron trapping into the gate insulator (GI) at the drain edge. Furthermore, the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula>) shift in the positive direction is caused by electrons flowing back to the source side and trapping into the buffer that induces source barrier lowing. The second stage of degradation, including a <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> shift in the negative direction and a decrease in the transconductance is caused by Joule heating induced negative bias temperature instability (NBTI). Furthermore, NBTI hardly occurs behind the pinch off in the channel and fixed oxide charge does not compensate the trapped electron at drain side which is induced in the first stage.

Bias-Dependence of Electroluminescence in AlGaN/GaN High-Electron-Mobility Transistors on SiC Substrate

This paper investigates bias-dependence of electroluminescence (EL) in an AlGaN/GaN HEMT fabricated on a SiC substrate. The HEMT exhibited a low-intensity reddish EL at the gate electrode at a drain voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> ) of 30 V, which was confirmed with combination of a top-side view using a CMOS sensor camera and a back-side view using a silicon-intensified CCD. As V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> was increased to 48 V, color change from low-intensity red to high-intensity white was accompanied with shift of the location from the gate to the drain edge. The changes in the EL are attributed to a shift of the high electric field from the gate to the drain electrode and a concentration of electric field near the drain edge.

Identifying the Properties of Traps in GaN High-Electron-Mobility Transistors via Amplitude Analysis Based on the Voltage-Transient Method

In this work, we developed the voltage-transient method to characterize the properties of traps in AlGaN/GaN high-electron-mobility transistors (HEMTs) in the OFF-state. By monitoring the drain voltage transients of the HEMTs at various temperatures, three types of trapping mechanism were identified: 1) buffer charge trapping, which occurred on a timescale of approximately 1 ms; 2) charge trapping in the AlGaN layer at the gate–drain edge with the energy level ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{a}$ </tex-math></inline-formula> ) of approximately 0.54 eV; and 3) surface charge trapping with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{a}$ </tex-math></inline-formula> of approximately 0.28 eV. In particular, we extracted accurate amplitudes for the first two trapping behaviors and studied the dependence of the trapping effect on the filling bias conditions. The results showed that the buffer charge trapping was primarily affected by the drain voltage, whereas the charge trapping on the drain side of the gate was affected by both the drain and gate voltages; these results were verified by drift-diffusion simulations. In addition, we observed the third trapping behavior, which was apparent in the measurement window beyond 308 K, thus demonstrating the advantages of our method for correctly and effectively monitoring the changes in the peaks in the time constant spectrum.

The Impact of Contact Position on the Retention Performance in Thin‐Film Ferroelectric Transistors

Here, the simulation of the physical fields in an n‐type ferroelectric thin‐film transistor (FeTFT) with a bottom contact bottom‐gate configuration is demonstrated. In the off‐state, the intensity of the lateral electric field in the space charge region near the edge of the drain electrode is several times higher than the coercive field of the ferroelectric film, pinning the direction of polarization near the drain electrode along the channel. While the FeTFT switches from off‐state to on‐state, the vertical component of polarization near the drain edge is stronger than other parts near the channel. This enhances the depolarization field in this area so that the retention performance of the on‐state is worse than the off‐state. These results and methods benefit FeTFTs and are also valuable for floating‐gate memory and light‐emitting field‐effect transistors.

On the Channel Hot-Electron’s Interaction With C-Doped GaN Buffer and Resultant Gate Degradation in AlGaN/GaN HEMTs

In this work, we report a critical semi- ON-state drain stress voltage above which the gate current increases significantly and degrades permanently in AlGaN/GaN high electron mobility transistors (HEMTs). The observed critical voltage was found to be channel field-dependent by analyzing devices with different field plate lengths and passivation thicknesses, along with different gate–drain distances. Besides field dependence, the critical voltage was found to be carrier energy dependent by comparing the performance of devices subjected to semi- ON-state stress with devices under OFF-state stress. Experimentation on HEMTs with different buffer carbon doping variations revealed the degradation phenomenon to be a function of carbon doping in the GaN buffer. Furthermore, detailed electric field and electron temperature analysis revealed the drain edge to be a hot spot in accelerating interaction of hot electrons with traps in the GaN buffer leading to gate current degradation. A mechanism based on hot electron–buffer trap interaction-induced thermoelastic stress buildup and subsequent defect formation in the GaN buffer is proposed to explain the observed performance degradations. Observations such as a significant rise in channel temperature and accumulation of mechanical stress in the GaN buffer validate the proposed mechanism. Finally, the processes responsible for degradation lead to catastrophic failure of the device for longer stress times by the formation of cracks and pits in the GaN buffer, as validated by the postfailure field emission scanning electron microscopy (FESEM) analysis.

Correlation between sidewall surface states and off-state breakdown voltage of AlGaN/GaN HFETs

Correlation between the sidewall surface states and off-state breakdown voltage of AlGaN/GaN heterojunction field effect transistors (HFETs) is investigated for the first time. HFETs explored in this work were realized on a variety of isolation features including conventional mesa, non-slanted fin, and slanted fin. The output and transfer characteristics of the devices from all categories of the fabricated AlGaN/GaN HFETs were studied, and a link between the separation of isolation feature sidewalls in the drain access region and the breakdown voltage was observed. Simulation results showed that by shrinking the width of the isolation feature geometry, the peak of the electric field at the drain edge of the gate is reduced as a result of tailoring its profile when a more resistive path is imposed on the drain access region. While HFETs realized on fins of smaller width benefit more from the depleting effect of acceptor sidewall surface states and consequently a higher off-state breakdown voltage, they suffer from a lower current density in the on-state. The slanted fin isolation feature geometry that we proposed here, while maintaining high breakdown voltage in the off-state, reduces the resistance in the on-state, which is represented by its highest Baliga's figure of merit among the three categories of isolation feature geometries. The proposed solution for achieving an improvement to the off-state breakdown voltage of AlGaN/GaN HFETs relies on a technology that has already been explored as a successful alternative for the realization of enhancement-mode transistors (i.e., with positive threshold voltage).

Suppression of charge trapping in ON-state operation of AlGaN/GaN HEMTs by Si-rich passivation

In this paper, we investigate the charge trapping in power AlGaN/GaN high electron mobility transistors which occurs in ON-state operation (V DS = 40 V, V GS = 0 V, I DS = 0.18 A mm−1). By analysing the dynamic ON-resistance (R ON) after OFF-state and ON-state stress in devices with different SiN x passivation stoichiometries, we find that this charge trapping can be largely suppressed by a high Si concentration passivation. Both potential probe and electroluminescence (EL) measurements further confirm that the stress can induce negative charge trapping in the gate–drain access region. It is shown that EL is generated as expected under the field plates at the gate edge, but is obscured by the field plates and is actually emitted from the device near the drain edge; hence care is required when using EL alone as a guide to the location of the high field region in the device. From temperature-dependent dynamic R ON transient measurements, we determine that the apparent activation energy of the measured ‘trap’ response is around 0.48 eV, and infer that they are located in the heavily carbon-doped GaN layer. Using the leaky dielectric model, we explain the response in terms of the hopping transport from the same substitutional carbon acceptor buffer dopants.

Analytical Study on a 700 V Triple RESURF LDMOS With a Variable High-K Dielectric Trench

A novel 700 V triple REduced SURface Field (RESURF) lateral double-diffused MOSFETs (LDMOS) with a variable high- K (VHK) dielectric trench for smart power applications is proposed and studied by TCAD simulations. Compared with conventional triple RESURF (CTR) LDMOS, the new structure features a composite high- K (HK) dielectric trench embedded in the drain edge. First, a higher HK dielectric layer is in the upper trench to suppress the high electric field ( E-field) under the drain by dielectric RESURF. Second, a lower HK dielectric is at the bottom of the trench to promote the depletion of the N-buffer layer and P-substrate, which increases the N-buffer doping concentration and thus reduces ON-resistance. The overall vertical bulk E-field distribution is modulated by the E-field peak generated at the position of varying K dielectric, which greatly improves breakdown voltage (BV). An analytical model of BV and vertical E-field taking account of the influence of the VHK dielectric trench is presented. Simulation results show that the proposed VHK TR LDMOS is able to obtain a 30.2% higher BV and a lower 15.4% R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON, sp</sub> than the CTR LDMOS. Moreover, the figure of merit (BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> ) of VHK TR LDMOS has doubled further breaking the lateral silicon limit.

Analysis of Dependence of Breakdown Voltage on Gate–Drain Distance in AlGaN/GaN HEMTs With High-k Passivation Layer

A 2-D analysis of OFF-state breakdown characteristics of AlGaN/GaN HEMTs with a high- k passivation layer is performed as a function of gate-to-drain distance L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> . The relative permittivity of the passivation layer ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> is changed from 1 to 60, and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> is changed from 1.5 to 10 μ\textm. It is shown that, in all cases with different L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> , the breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> increases as ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> increases. When a deep-acceptor density in an Fe-doped buffer layer N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DA</sub> is 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17 </sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and the gate length is 0.3 μm, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> is determined by buffer leakage current at ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> ≥ 30 before impact ionization dominates. Hence, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> is similar at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> = 3-10 μm, and the increase rate in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> from L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> = 1.5 μm is about 50% even at ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> = 60. However, when N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DA</sub> is 2×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> , V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> is determined by impact ionization of carriers even at ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> ≥ 30 because the buffer leakage current is reduced. V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> becomes about 500, 930, 1360, and 1650 V for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> = 1.5, 3, 5, and 7 μm, respectively, at ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> = 60. These voltages correspond to gate-to-drain average electric fields of about 3.3, 3.1, 2.7, and 2.3 MV/cm, respectively. Particularly, for short L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> , the electric field profiles between the gate and the drain are rather uniform. However, in the case of L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> = 10 μm, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> is about the same as that (1650 V) of L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> = 7 μm, suggesting that the electric field at the drain edge of the gate becomes a critical value before the high electric field region extends to the drain enough. This may be a limitation to increase V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> by using a high- k passivation layer in this case. However, it can be said that, to improve V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> further at long L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> , such as 10 μm, the combination of field plate or using a higher ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> material may be effective because both of them decrease the electric field at the drain edge of the gate.

The effect of high-k passivation layer on off-state breakdown voltage of AlGaAs/InGaAs HEMT

In this paper, the effects of different relative permittivity (εr) of the passivation layer on off-state breakdown voltage of AlGaAs/InGaAs HEMTs are analyzed by ISE-TCAD. It is shown that as εr value increases, the off-state breakdown voltage increases. When the εr value increased to 80, the off-state breakdown voltage increased from 17.23V to 24.13V by 40.9%. This is because the peak value of electric field at the proximity of gate edge is reduced with the increase of εr value and it can lead to the improvement of the off-state breakdown voltage of device. Meanwhile, the electric field peak value near the drain edge increases with the increase of the εr value, leading to an increase in the ionization probability of electron-hole ionization under the the grid-drain area. In addition, the results also show that the channel current (IDS) and transconductance (gm) of the device are slightly reduced by the passivation layer with a high εr value, while the specific channel on-resistance is hardly degraded. Therefore, the passivation layer with a high εr value can effectively improve the breakdown voltage of the device without sacrificing the DC characteristics of the device.

Drain-Bias-Dependent Study of Reverse Gate-Leakage Current in AlGaN/GaN HFETs

Reverse gate-leakage of the AlGaN/GaN heterostructure field-effect transistors (HFETs) is studied at different values of drain–source voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> ), ranging from 0 to 10 V. Throughout the investigated range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> , the reported analysis confirms the applicability of the Fowler–Nordheim (FN) tunneling as the dominant contributor to the gate-leakage for reverse gate biases until the onset of the threshold voltage. Device simulations were performed using Comsol Multiphysics to estimate the electric field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E\,\,$ </tex-math></inline-formula> ) across the polar III-nitride barrier layer at different positions along the gate length. We observe that the FN tunneling takes place predominantly corresponding to the average electric field observed to be close to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} $ </tex-math></inline-formula> at the center of the gate for lower values of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> , whereas at larger values of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> , FN tunneling corresponding to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}$ </tex-math></inline-formula> only at the drain edge of the gate seems poised to deliver the gate-leakage current. In formulating the FN tunneling, the value of the electron effective mass is selected consistently within an acceptable range for analyzing gate-leakage. Investigating the applicability of FN tunneling in explaining the reverse gate-leakage current of AlGaN/GaN HFETs for the aforementioned values of gate to source voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {GS}}$ </tex-math></inline-formula> ) not just at zero <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> , but across a range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> values, seems to offer a more convincing argument for the hypothesis on tunneling through small leakage zones.