Abstract
In this paper, we investigate the charge trapping in power AlGaN/GaN high electron mobility transistors which occurs in ON-state operation (V DS = 40 V, V GS = 0 V, I DS = 0.18 A mm−1). By analysing the dynamic ON-resistance (R ON) after OFF-state and ON-state stress in devices with different SiN x passivation stoichiometries, we find that this charge trapping can be largely suppressed by a high Si concentration passivation. Both potential probe and electroluminescence (EL) measurements further confirm that the stress can induce negative charge trapping in the gate–drain access region. It is shown that EL is generated as expected under the field plates at the gate edge, but is obscured by the field plates and is actually emitted from the device near the drain edge; hence care is required when using EL alone as a guide to the location of the high field region in the device. From temperature-dependent dynamic R ON transient measurements, we determine that the apparent activation energy of the measured ‘trap’ response is around 0.48 eV, and infer that they are located in the heavily carbon-doped GaN layer. Using the leaky dielectric model, we explain the response in terms of the hopping transport from the same substitutional carbon acceptor buffer dopants.
Highlights
Power AlGaN/GaN high electron mobility transistors (HEMTs) have attracted wide attention for their outstanding performance with high breakdown voltage and low ON-resistance [1]
The devices under test are AlGaN/GaN HEMTs fabricated on 150 mm diameter GaN-on-Si wafers
A 70 nm low-pressure chemical vapour deposition (LPCVD) SiNx passivation is placed above the GaN cap and two 300 nm plasma-enhanced chemical vapour deposition (PECVD) SiNx layers are deposited between the source fieldpates
Summary
Power AlGaN/GaN high electron mobility transistors (HEMTs) have attracted wide attention for their outstanding performance with high breakdown voltage and low ON-resistance [1]. Charge trapping remains a major issue, resulting in current collapse and efficiency losses. In power GaN transistors where a carbon-doped buffer layer is used to prevent the punch through effect [4] and to suppress breakdown, the CN carbon acceptor (Ea = 0.8 ± 0.2 eV) is reported as the major buffer trap. Several measures have been adopted to minimize current collapse, i.e. field plates [5], epitaxy [6] and SiNx passivation layers [7]
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