Drain Disturbance Research Articles

Behaviour of Three Test Embankments Taken to Failure on Soft Clay

This article compares and analyses the behaviour of three test embankments. The soil foundation consisted of normally consolidated clay overlain by a thick sand surface layer. The embankments were rapidly constructed until failure, which occurred after approximately 50 days. Two of the embankments were reinforced, one including prefabricated vertical drains (PVD), while the third had neither reinforcement nor PVDs. The two reinforced embankments presented similar net embankment heights (fill thickness minus average settlement) at failure, owing to the similarity in the undrained strength values of the two clay layers. The test embankment with PVDs showed that this drainage feature improved overall behaviour but the benefit was less than suggested in the literature, owing to the low coefficient of consolidation of the normally consolidated clay, rapid construction and drain disturbance effects. Numerical analyses of the test embankment with PVDs showed good overall agreement between measured and computed values and confirmed overall field observations. The embankment without reinforcement and PVDs reached a greater embankment height than the two reinforced embankments, owing to its greater clay strength.

Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: Vg = 6 V, Vd = 7 V and Vg = -7 V, Vd = 10 V, respectively), greater tolerable gate and drain disturbance (Vt shift 108 s for 13% charge loss), and excellent endurance performance (after 104 P/E cycles with a memory window of 3 V).

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

In this paper, highly reliable wrapped-select-gate (WSG) silicon–oxide–nitride–oxide–silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 µs/5 ms) and low programming current (3.5 µA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

Novel coexisted sol-gel derived poly-Si-oxide-nitride-oxide-silicon type memory

The authors use a very simple sol-gel spin coating method at 900°C and 1min rapid thermal annealing to fabricate three different poly-Si-oxide-nitride-oxide-silicon-type flash memories. The memory windows estimated from the curve of drain current versus applied gate voltage are 3, 3.3, and 4V for (i) HfO2 thin film, (ii) hafnium silicate nanocrystal, and (iii) coexisted hafnium silicate and zirconium silicate nanocrystal memory, respectively. Together with the measurement from gate disturbance and drain disturbance on these fabricated devices, the coexisted nanocrystal devices exhibit better reliability than both the thin film type memory and single nanocrystal type memory.

Impact of Channel Dangling Bonds on Reliability Characteristics of Flash Memory on Poly-Si Thin Films

In this letter, we fabricated the poly-Si-oxide-nitride-oxide-silicon (SONOS)-type Flash memories on polycrystalline-silicon thin films and found that dangling bonds presented along the grain boundaries in the channel significantly influence their reliability characteristics in the aspects of charge storage, drain disturbance, and gate disturbance. Employing a powerful defect passivation technique, i.e., NH3 plasma treatment, the charge storage capability was clearly observed to be remarkably improved. Even so, the hydrogenated polycrystalline-silicon thin-film transistors (poly-Si-TFTs) still suffered from serious drain and gate disturbances, which exhibited behaviors that are quite specific and undoubtedly distinct from those observed in the conventional SONOS-type memories on single crystalline substrates

Highly Reliable Multilevel and 2-bit/cell Operation of Wrapped Select Gate (WSG) SONOS Memory

In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mus/5 ms) and low programming current (3.5 muA) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (>150degC) and good endurance (>104) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application

Realization of Two-bit Operation by Bulk-biased Programming Technique in SONOS NOR Array with Common Source Lines

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

Fault Models and Test Procedures for Flash Memory Disturbances

Disturbances are special type of faults that are unique to flash memories. Causes of the disturbances are defects within the insulating layers of the memory element. These defects result in abnormal behavior of a memory cell under specific conditions. This paper describes characteristics of these defects as well as their manifestation as DC-Programming, DC-Erasure, and Drain Disturbance. We develop fault models to capture the behavior of faulty flash memories. We introduce three different fault models based on the underlying defects in a memory cell. These models are: Simple, Exclusive and General Fault model. Further, we develop test algorithms that detect disturbance faults under each of the fault models. The test algorithms reported in this paper for the simple fault model for each type of disturbance require optimal number of program, read, and flash operationss where as the algorithms for the remaining two fault models require near optimal number of these operations.

New self-adjusted dynamic source multilevel p-channel flash memory

In this work a new multilevel programming approach employing the new self-adjusted dynamic source (SADS) structure for p-channel flash memory is studied. The memory unit is composed of a current source and a p-channel stacked-gate transistor. Using SADS structure, the final source voltage, which is not grounded, is found to be dependent on the applied drain voltage. Programmed threshold voltage is observed to be proportional to the final source voltage. Adjusting drain voltages during programming results in the predictable multilevel threshold voltages due to the self-adjusted dynamic source mechanism. The programming drain current in p-channel flash memory can be limited to a low level to achieve low power programming by adjusting the conducting current of the current source. Furthermore, the drain disturbance, which alters the stored charge of other memory cells, can be suppressed in the SADS structure by shutting off the current source and employing negative word line voltages on the unselected cells.

Simulation, fabrication and characterization of a 3.3 V flash ZE 2PROM array implemented in a 0.8 μm CMOS process

This paper describes a Zener based flash memory cell (ZE 2PROM), programmed from hot electrons generated by a heavily doped reverse biased p +n + junction attached to the drain. The cell can be implemented in a NOR type memory array. It uses an orthogonal write technique to achieve fast programming with low power dissipation and reduced drain disturbance. The modeling of the charge transfer behavior of the flash ZE 2PROM cell is also done to describe the charging and discharging of the floating gate during programming and erasing. The flash ZE 2PROM arrays were implemented in a 0.8 μm lithography CMOS process flow in which the n-LDD step was replaced with a one sided p + boron implant with a doping level of ∼10 19 cm −3. This minor change to a standard CMOS process, makes the concept highly attractive for embedded memory applications. A programming time of 850 ns at 3.3 V supply was achieved on fabricated test devices.