Drain Avalanche Hot-carrier Stress Research Articles

65 nm CMOS 기술에서 소자 종류에 따른 신뢰성 특성 분석

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond <TEX>$0.18{\mu}m$</TEX> CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.

Study on Time Constants of Random Telegraph Noise in Gate Leakage Current Through Hot-Carrier Stress Test

Capture and emission time constants obtained from random telegraph noise in gate leakage current ( Ig RTN) are studied by characterizing an intentionally created trap in thin gate oxide (2.6 nm) in metal-oxide-semiconductor field-effect transistors (MOSFETs). The single oxide trap was generated at the drain edge region in virgin nMOSFETs by drain-avalanche hot-carrier stress. By analyzing the location and energy level of the trap extracted from the experimental data, the time constants of high and low current levels in Ig RTN were found to be capture and emission times, respectively.

Temperature Dependence of Performance and Hot-Carrier Immunity in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

The temperature dependence of the performance and hot-carrier instability of excimer-laser-crystallized low-temperature polycrystalline silicon thin-film transistors (TFTs) is described. The dependence of the TFT's performance on temperature indicates three characteristics: 1) electron mobility decreases with decreasing temperature, whereas the hole mobility is temperature independent; 2) off-leakage current decreases with decreasing temperature; and 3) threshold voltage increases with decreasing temperature. To consider the origin of the temperature dependence of the threshold voltage, estimation using the trap state density obtained by capacitance–voltage analysis is carried out. The main origin is concluded to be the change in the density of occupied defect states owing to the temperature dependence of the Fermi level. Contrary to the mobility, current under the drain-avalanche hot-carrier stress is found to be higher in a cold environment. The more serious current degradation after the stress in a cold environment is attributable to the reduced scattering of hot carriers owing to less lattice vibration.

Defect Generation and Severity Comparison of Negative Bias Temperature Stress-Induced Degradation on 90 nm p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Different Oxide Thicknesses

The aim of this study is to investigate negative bias temperature (NBT) stress-induced p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET) degradation in 90 nm complementary metal–oxide–semiconductor (CMOS) technology. The study especially focuses on the effects of NBT stress on the pMOSFETs with different oxide thicknesses, such as 16, 31, and 68 Å, and on its degree of severity compared with the degradation induced by drain avalanche hot-carrier (DAHC) stress and channel hot-carrier (CHC) stress at the same biased voltage and temperature. We find that although NBT-induced damage is more serious in devices with a thicker silicon oxynitride (SiON) dielectric, the predicted lifetimes reveal that the pMOSFETs with thinner oxide layers will be more critical in meeting the reliability requirements. Very similar results are also found for the comparison of NBT stress and CHC stress, i.e., although CHC stress is more severe than NBT stress under the test conditions, NBT stress is more critical under operational conditions, while DAHC stress only causes very minor degradation. Additionally, it is always interesting and important to understand degradation mechanisms. Therefore the gated-diode (GD) method is used in this study to determine the cause of NBT stress-induced degradation. Many insights are found by analyzing the results of the GD measurements and are reported in this work.

Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation

The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.

Trend transformation of drain-current degradation under drain-avalanche hot-carrier stress for CLC n-TFTs

Continuous-wave green laser-crystallized (CLC) single-grain-like polycrystalline silicon n-channel thin-film transistors (poly-Si n-TFTs) demonstrate the higher electron mobility and turn-on current than excimer laser annealing (ELA) poly-Si n-TFTs. Furthermore, high drain voltage accelerates the flowing electrons in n-type channel, and hence the hot-carriers possibly cause a serious damage near the drain region and deteriorate the source/drain (S/D) current. In this study, at high drain stress voltage, it appears that CLC TFT was degraded in the initial stress time (before 50 s), but the drain current was enhanced after 50 s. After 50 s stress time, the amount of grain boundary trap states near the drain side was getting large and the reflowing holes damaged the source region or injected into gate oxide near source side as well.

Hot Carrier Reliability of ALD HfSiON Gated MOSFETs with Different Compositions

Metal-oxide-semiconductor field-effect transistors (MOSFETs) in-corporating hafnium-silicate (HfSiON) dielectrics with different compositions were fabricated and investigated for hot carrier reli-ability. The experimental results reveal that the channel hot carrier (CHC) stress is worse than drain avalanche hot carrier (DAHC) stress. Moreover, the experimental results also show that the in-crease of oxide trapped charges (ΔNot) depends on Hf content and is about one order of magnitude larger than that of interface traps (ΔNit) after CHC or DAHC stress. Finally, some important interfa-cial parameters, including ΔNit, ΔDit and ΔNot, have also been characterized through the transconductance and subthrehsold swing (SS) methods.

Impact of the strained SiGe source/drain on hot carrier reliability for 45nm p-type metal-oxide-semiconductor field-effect transistors

In this letter, the impact of the uniaxial strain SiGe source/drain (S/D) on hot carrier reliability in 45nm p-type metal-oxide-semiconductor field-effect transistor is investigated in detail. We find that the extra mechanical stress deteriorates the gate oxide and/or generates interface states significantly, resulting in the hot carrier degradation dominantly driven by the drain avalanche hot carrier stress (Vg=1∕2Vd), as opposed to the channel hot electron stress (Vg=Vd), the well-known dominant mechanism for hot carrier degradation in the conventional deep submicron devices. A model to explain the mechanism of these observations is proposed.

Accelerated Negative-Bias Temperature Degradation in Low-Temperature Polycrystalline-Silicon p-Channel TFTs Under Dynamic Stress

The degradation mechanism in p-channel polysilicon thin-film transistors under negative-bias temperature (NBT) stress and pulse stress, which alternates NBT stress and drain-avalanche hot carrier (DAHC) stress, was investigated. An analysis of recovery effects and activation energy suggests that the device degradation under dc-NBT stress is explained by a reaction-diffusion model and limited by hydrogen diffusion. These features are also observed in the case of the device degradation under pulse stress. Pronounced degradation occurs not after DAHC stress application (electron injection) but after NBT stress application (hole injection). NBT stress degradation is locally accelerated after DAHC stress application because the effective gate voltage negatively increases due to trapped electrons during DAHC stress. The trap states and positive charges that were generated by this accelerated NBT stress are considered to be the main cause of device degradation under pulse stress.

High-Quality CVD SiO2 Interfacial Layer Prepared by Cyclic Deposition with O2 Plasma Treatment

We have developed a new process, cyclic deposition with plasma treatment (C-DOP), to obtain a high-quality interfacial layer (IL) that can be applied to low-temperature poly-Si thin-film transistors (TFTs). The C-DOP process uses sequential deposition followed by plasma treatment. By increasing radio frequency power during plasma treatment, the film becomes denser, and the density of the C-DOP-formed becomes close to that of thermal oxide. The amounts of residual impurities, such as , H, and C, are decreased by the C-DOP process. We applied the C-DOP process to form a thin IL. It is effective in suppressing the flatband voltage shift due to Fowler–Nordheim negative stress when the IL thickness is more than . By applying the C-DOP-formed IL to poly-Si TFTs, drain-current degradation due to drain-avalanche hot-carrier stress is successfully suppressed, and the time to 10% reduction of the drain current is prolonged by 1 order of magnitude.

A New Model for Device Degradation in Low-Temperature N-Channel Polycrystalline Silicon TFTs Under AC Stress

Enhanced device degradation of low-temperature n-channel polycrystalline thin-film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater severity of degradation. Moreover, a lightly doped drain (LDD) TFT is less strongly affected, and the effect is dominated by accumulated drain-avalanche hot-carrier (DAHC) stress. It was also found that differences between the electric field in the respective channel regions are responsible for the different degradation properties of SD and LDD TFTs. It was shown that the severe degradation under ac stress in an SD TFT is caused by increased DAHC stress, to which electrons emitted from the trap states when the TFT is turned off make significant contributions.

Small-signal gate-to-drain capacitance of MOSFET as a diagnostic tool for hot-carrier induced degradation

In this paper a method for the study of hot-carrier induced charge centers in MOSFETs based on a small-signal gate-to-drain capacitance measurement is described. Numerical modeling and simulation is used to provide an understanding of the effects of spatially localized trapped carriers and interface states on this capacitance. Experimental gate-to-drain capacitance results are presented and compared with charge pumping measurements. This method is used to investigate hot-carrier degradation of n- and p-channel MOSFETs after drain avalanche hot-carrier stress conditions. It is concluded that under this stress condition the degradation of both n- and p-channel devices is due to the trapping of majority carriers and the generation of acceptor type interface states in the top half of the silicon bandgap.