Small-signal gate-to-drain capacitance of MOSFET as a diagnostic tool for hot-carrier induced degradation

Abstract

In this paper a method for the study of hot-carrier induced charge centers in MOSFETs based on a small-signal gate-to-drain capacitance measurement is described. Numerical modeling and simulation is used to provide an understanding of the effects of spatially localized trapped carriers and interface states on this capacitance. Experimental gate-to-drain capacitance results are presented and compared with charge pumping measurements. This method is used to investigate hot-carrier degradation of n- and p-channel MOSFETs after drain avalanche hot-carrier stress conditions. It is concluded that under this stress condition the degradation of both n- and p-channel devices is due to the trapping of majority carriers and the generation of acceptor type interface states in the top half of the silicon bandgap.