Downconversion Receiver Research Articles

Interference cancellation and frequency down-conversion receiver based on Sagnac loop

Compared with traditional duplex technology, in-band full-duplex (IBFD) technology can improve spectrum utilization, network capacity and system throughput. However, strong co-frequency signals from adjacent transmission antennas may cause the received signals to be flooded, significantly degrading the communication performance. In addition, frequency down-conversion is an essential function of the receiver, and the subsequent image interference will also block the receiver. A self-interference cancellation (SIC) and image rejection down-conversion receiver based on the Sagnac loop is presented to solve these two problems. The self-interfering signals are eliminated using polarization control and delay matching in the optical domain. Image rejection is achieved by adjusting the DC bias of the modulator. Therefore, all operations required for the above two functions are implemented using optical methods. The theoretical and experimental validation is carried out. The results show that a self-interference cancellation depth of over 43 dB and an image interference rejection ratio of 45 dB is achieved for single-tone signal after frequency down-conversion. For 16 quadrature amplitude modulation (16QAM) signals with a bandwidth range from 20 MHz to 50 MHz, the self-interference cancellation depth exceeds 26 dB, and the image interference rejection ratio exceeds 30 dB.

Interference Cancellation and Frequency Down-Conversion Receiver Based on Sagnac Loop

Interference Cancellation and Frequency Down-Conversion Receiver Based on Sagnac Loop

LO Chain (×12) Integrated 190-GHz Low-Power SiGe Receiver With 49-dB Conversion Gain and 171-mW DC Power Consumption

A 190-GHz mixer-based down-conversion receiver realized in a 130-nm SiGe BiCMOS technology featuring high-speed heterojunction bipolar transistors (HBTs) with ( $f_{\text {T}}$ , $f_{\text {max}}$ ) = (300, 500) GHz is presented. The core part of the receiver consists of a low-noise amplifier (LNA), an active tunable fundamental mixer, an intermediate frequency (IF) buffer amplifier (BA), and an active inverse balun. A wideband, high conversion gain (CG) local oscillator (LO) chain is integrated to make the receiver suitable for applications requiring tunable LO, which contains a multiplier with a multiplication factor of 12 ( $\times 12$ ) and a driver amplifier. To exploit the best possible performance with ultralow dc power consumption ( $P_{\text {dc}}$ ), the mixer and LNA transistors operate at forward-biased base–collector junction voltage ( $V_{\text {BC}}$ ). With a fixed IF frequency at 1 GHz, this receiver exhibits a peak CG of 49 dB with a 14-dB tuning range and a minimum single-sideband noise figure (NF) of 16.5 dB, consuming only 29-mW static dc power for the core part and 171 mW overall, including the LO chain. Within the CG tuning range, this receiver achieves a 6-dB RF bandwidth (BW) from 25 to 32 GHz. Compared with previously reported receivers at similar frequencies, the highest CG and the lowest $P_{\text {dc}}$ with highly competitive performance in terms of BW, CG tuning range, 1-dB output compression point, and NF have been achieved.

Adaptive IQ Mismatch Compensation in Time-Domain Using Frequency-Domain Observations

The imbalance between in-phase (I) and quadrature (Q) branches of quadrature down-conversion receivers creates interference between the mirror frequencies in baseband. We introduce two new adaptive algorithms for compensating frequency-dependent IQ imbalance in orthogonal frequency-division multiplexing (OFDM) systems. The proposed algorithms utilize frequency-domain observations to update filter weights of a time-domain IQ mismatch compensator (IQMC) based on a mini-batch gradient descent search approach. The update rule in the first algorithm is based on the kurtosis criterion, which is a blind adaptation method. The second algorithm is based on minimizing the Euclidean distance (ED) between the frequency-domain impaired signal and the known received reference signal, which is a pilot-aided method. A low-complexity method is introduced to obtain the gradient of cost functions that are only based on the IQMC coefficients and the frequency-domain observations. Numerical results demonstrate that the proposed algorithms reduce IQ imbalance considerably. The proposed adaptation schemes outperform conventional time-domain IQMC schemes in high signal-to-noise ratio region and also use a much smaller number of adaptation parameters than the previous frequency-domain IQMC methods.

A Fully Integrated K-Band Dual Down-Conversion Receiver for Radar Applications in 90 nm CMOS

A fully integrated K-band dual down-conversion receiver for phased array radar applications in 90 nm CMOS is presented. The receiver utilizes the dual down-conversion architecture to achieve superior performance. The integrated 1.15 GHz image-rejection filter (IRF) provides enough wideband (22 MHz) image rejection ratio at 140 MHz offset before the second down-conversion by utilizing the Q-enhancing and frequency staggering techniques to compensate the component loss. The low noise amplifier realizes the single-to-differential-ended conversion at the input with a transformer and achieves good common-mode rejection. The 70 MHz intermediate frequency baseband consists of two cascaded 3rd-order band-pass active RC filters (BPFs) and one automatic gain control (AGC) loop, with the integrator frequency compensation technique to lower down the requirements on the embedded Op-Amps. Two phase-locked loop (PLL) frequency synthesizers are integrated to provide the local oscillation (LO) signals for the down-conversions, where the matching of the charge-pump is improved by adding one extra current compensation branch. The measurements of the prototype show that the receiver converts the targeted mm-wave signal to 70 MHz intermediate frequency while achieving 8.3 dB noise figure (NF), 51-95 dB variable gain range and >45 dB image rejection ratio at 140 MHz offset with >22 MHz signal bandwidth. The receiver draws 74 mA current (excluding 2 PLLs) from the 1.2 V power supplies and occupies a core area of 4.58 × 0.53mm 2 (excluding 2 PLLs).

Spectrum Sensing in SIMO Cognitive Radios Under Primary User Transmitter IQ Imbalance

In this paper, we model the received signal of a single-input-multiple-output (SIMO) cognitive radio with in-phase and quadrature imbalance (IQI) in the transmitter. Then, the spectrum sensing problem is formulated as a composite hypothesis testing problem. We propose two new eigenvalue-based detectors based on the likelihood ratio test (LRT), Rao and Wald frameworks, i.e., the resultant LRT leads us to the Wald test. For the proposed Rao test, we find closed-form expressions for false alarm and detection probabilities under noise variance uncertainty in order to get the level of desired false alarm probability $p_{\text{fa}}$ , i.e., it is called a level $p_{\text{fa}}$ test. This is required for nonconstant false alarm rate (non-CFAR) such as the Rao test to guarantee that the obtained false alarm rate is always below a required level $p_{\text{fa}}$ . Additionally, an analytical formula for the probability of false alarm of Wald test is presented to confirm our simulation results. In this case, the proposed Wald detector is a size $p_{\text{fa}}$ test, called a CFAR detector. Detection performances of the proposed detectors are compared in different scenarios by extensive Monte Carlo simulations. It is shown that the Wald detector outperforms the proposed Rao one. Also, we show that the effects of transmitting IQI can be considered as a signal-to-noise ratio factor, just affecting the detection performance. Also, our performance results show that the proposed Wald detector is fairly robust to the receiver IQI when direct down-conversion receivers are exploited.

A low-power high-sensitivity single-chip receiver for NMR microscopy

In this paper, we present a fully-integrated receiver for NMR microscopy applications manufactured in a 0.13μm CMOS technology. The design co-integrates a 10-turn planar detection coil together with a complete quadrature, low-IF downconversion receiver on a single chip, which operates from a single 1.5V supply with a total power dissipation of 18mW. The detector’s measured time-domain spin sensitivity is 3×10131Hspins/Hz at 7T. Additionally, the paper discusses two important aspects of NMR microscopy using planar detection coils: the link between the detection coil’s spin sensitivity and the achievable image SNR and the correction of image artifacts induced by the inhomogeneous sensitivity profile of planar detection coils. More specifically, we derive analytical expressions for both the theoretical image SNR as a function of the coil’s spin sensitivity and the sensitivity correction for a known coil sensitivity profile in CTI MR imaging experiments. Both expressions are validated using measured data in the imaging section of the paper. Thanks to the improved spin sensitivity of the utilized integrated receiver chip compared to a previously presented design, we were able to obtain sensitivity corrected images in a 7T spectroscopy magnet with isotropic resolutions of 9.6μm and 5μm with single-shot SNRs of 37 and 15 in relatively short imaging times of 4.4h and 24h, respectively.

Digitally Enhanced Wideband I/Q Downconversion Receiver With 2-Channel Time-Interleaved ADCs

The interesting concept of employing in-phase/quadrature (I/Q) downconversion together with time-interleaved analog-to-digital converters allows digitizing very wide instantaneous radio-frequency (RF) bandwidths (BWs) and grants enhanced flexibility in accessing and processing the RF spectrum. Such a structure also inevitably suffers from performance degradation due to the analog components' nonidealities, e.g., frequency response mismatches (FRMs), that ultimately lead to spurious mismatch components that limit the system's dynamic range. Available solutions developed for I/Q mismatches or time-interleaving mismatches alone are not compatible for correcting the FRM spurs in such joint I/Q time-interleaved converter (IQ-TIC) architecture. This brief proposes novel blind FRM identification and correction solutions that are able to suppress all the associated spurs in the considered wideband IQ-TIC architecture. The proposed digital correction solutions are tested and verified using measured hardware data obtained from an experimental platform, exhibiting good FRM spur correction performance with instantaneous BW on the order of 800 MHz. These developments pave the way toward 5G radio communication devices and systems where instantaneous BWs on the order of 1 GHz are envisioned at centimeter- and millimeter-wave frequency bands.

Analysis and Design of a 0.6- to 10.5-GHz LNTA for Wideband Receivers

A low-noise transconductance amplifier (LNTA) for wideband receivers based on a $g_{m} $ -boosted current mirroring topology that operates over 0.6- to 10.5-GHz is presented. $g_{m}$ boosting relaxes the $G_{m}$ and $S_{11} $ bandwidth (BW) tradeoff and the noise figure (NF) and input matching tradeoff. The active feedback synthesizes a second-order input impedance profile that further extends the $S_{11}$ BW. Despite the high $G_{m} $ obtained over large BW, high linearity is maintained through the predistortion inherent in the current mirroring topology. The LNTA is used in a 65-nm CMOS wideband channelizing iterative downconversion receiver targeting spectrum and signal analysis for cognitive radio and performs active signal splitting across two paths with a total postlayout simulated $G_{m} $ of 242 mS (170 and 72 mS in paths 1 and 2, respectively). $S_{11}$ BW and $G_{m} $ BW both exceed 10.5 GHz. Minimum LNTA NFs simulated in the two paths are 4 and 4.8 dB, respectively. Simulated wideband IIP3 and blocker P1dB are +6 and +1.5 dBm, respectively. Measurements of a direct conversion receiver in path 2 closely match simulations.

SiGe BiCMOS high‐gain and wideband differential intermediate frequency amplifier for W‐band passive imaging single‐chip receivers

This thesis presents solutions and studies related to the design of reconfigurable and wideband receiver circuits for system-on-chip (SoC) radiometer front-ends within the millimetre-wave (mm-wave) range. Whereas many of today’s mm-wave front-ends are bulky and costly due to having discrete RF components, single-chip receiver modules could potentially result in a wider use for emerging applications such as wireless communication, short range radar and passive imaging security sensors if realised with adequate performances and at a lower cost. Three main topics are considered in this thesis, monolithic integration of low-loss RF-MEMS (Dicke) switch networks and switched LNAs in MMIC/RFIC foundry processes, designs of SiGe wideband (IF) amplifier and broadband power detectors up to W-band (75-110 GHz).Low-loss and high isolation GaAs and SiGe RF-MEMS switch networks were designed and characterised for the 30-110 GHz range. A GaAs MEMS Dicke switch network has a measured minimum loss of 1 dB and maximum isolation of 19 dB at 70-96 GHz, respectively, making it a potential candidate in Dicke switched radiometer receivers. Furthermore, single-chip 30 GHz and W-band MEMS Dicke switched LNA designs have been realised for the first time in SiGe BiCMOS and GaAs mHEMT processes, respectively.For a targeted 94 GHz passive imaging application two different receiver topologies have been investigated based on direct-detection and direct-conversion (heterodyne) architectures. An optimised detector design fabricated in a 0.13 μm SiGe process achieves a more wideband input matching than earlier silicon W-band detectors and is competitive with reported III-V W-band detectors in terms of a higher responsivity and similar NEP.A SiGe 2-37 GHz high-gain differential (IF) amplifier design achieves a more wideband matching and an order of magnitude higher linearity than a recent single-ended SiGe LNA. The SiGe IF amplifier was integrated on-chip with a power detector in a 5-35 GHz IF section. Their broadband properties compared with other IF amplifier/detector RFICs, make them suitable for W-band down-conversion receivers with a larger pre-detection bandwidth and improved sensitivity. The experimental results successfully demonstrate the feasibility of the SiGe 5-35 GHz IF section for high performance SoC W-band radiometers using a more wideband heterodyne receiver architecture.

A SAW-Less First Folded-Conversion Second Down-Conversion Receiver for Multistandard Broadcasting Radio Applications

A surface-acoustic-wave-less first folded-conversion and second down-conversion receiver for the AM/FM/digital radio mondiale (DRM)/digital audio broadcasting (DAB) radio standards is presented. This architecture is more suitable for broadcasting radio with ultra-narrow signal bandwidth since it relaxes the requirement on the local area (LO) generator by decreasing its tuning range. To reduce the blockers and out-of-band (OB) interferers, current amplifying and polyphase filters are introduced simultaneously. An inverter-based switched capacitor array technique is proposed in voltage-controlled oscillator (VCO) design to isolate the noise from the substrate. With a single VCO, the receiver can cover the frequency range from 100 kHz to 1.5 GHz. Without the RF pre-filters, the in-band ${\rm IIP}_{3}$ is 1.5 dBm, and the OB ${\rm IIP}_{3}$ is up to 17.4 dBm. The LO phase noise in the worst case is $-$ 119 dBc/Hz@1 MHz. The chip is fabricated in a 0.18- $\mu{\hbox{m}}$ CMOS technology, and mounted on a QFN package. It consumes only 86.4 mW under 1.8-V supply. To our best knowledge, this is first receiver reported thus far that supports all four AM/FM/DRM/DAB standards.

Clock Jitter Compensation in High-Rate ADC Circuits

Clock timing jitter refers to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acquired samples in the midst of random noise. We propose low-complexity digital signal processing methods for estimating the jitter in real-time for direct downconversion receivers at high sampling rates. We also propose adaptive compensation methods for the jitter and analyze the performance of the proposed techniques in some detail as well as through simulations.

Integrated active tracking detector for MRI-guided interventions

We present a fully integrated detector suitable for active tracking of interventional devices in MR-guided interventions. The single-chip microsystem consists of a detection coil, a tuning capacitor, an intermediate frequency downconversion receiver, and a phase-locked-loop-based frequency synthesizer. Thanks to the integrated mixer, the chip output stage delivers an analog frequency-downconverted NMR signal in the frequency range from 0 to 200 kHz. The microchip, realized in a standard complementary metal oxide semiconductor technology, has a size of 1 × 2 × 0.74 mm(3) and operates at a frequency of 63 MHz (i.e., in 1.5 T clinical scanners). Tests in a standard clinical scanner demonstrate the compatibility of the complementary metal oxide semiconductor microchip with clinical MRI systems. Using a solid sample of cis-polyisoprene having a size of 1 × 1.9 × 0.8 mm(3) as internal signal source, the detector achieves a three-dimensional isotropic spatial resolution of 0.15 mm in a measuring time of 100 ms.

A 160-GHz low-noise downconversion receiver front-end in a SiGe HBT technology

A 160-GHz SiGe-HBT (Heterojunction Bipolar Transistor) down-conversion receiver front-end for use in active millimeter-wave imaging arrays and D-band communication applications is presented. The monolithic front-end consists of a three-stage low-noise amplifier providing 24 dB of gain and a Gilbert-cell mixer capable of operating from a −8-dBm LO signal. A fully differential architecture compatible with balanced on or off-chip antennas is used to avoid the need for on-chip baluns in antenna-integrated applications. The implemented downconversion front-end consumes 50 mA from a 3.3 V supply and requires a 0.1 mm2 die area (excl. pads) per channel. With a 160-GHz input signal and an Intermediate Frequency (IF) of 1 GHz, the implemented front-end yields a 25-dB conversion gain, a −30-dBm input compression point, and a 9-dB/7-dB (with/without auxiliary on-chip input balun) system noise figure.

Architectural solution for second-order intermodulation intercept point improvement in direct down-conversion receivers

Second-order intermodulation is a great drawback in zero-intermediate frequency (IF) receivers. Many complex techniques for distortion cancelling have been proposed in the literature. In this study, the authors propose a simple architectural solution for second-order intermodulation intercept point (IIP2) improvement and also theoretically and experimentally demonstrate the high rejection level abilities. To determine its performance, a classical in-phase and quadrature (IQ) demodulator was also designed and used as a reference. In order to compare their non-linear behaviour in the presence of interfering signals, two types of zero-IF demodulators were tested in this work in terms of error vector magnitude and bit error rate. This study shows that by using the three-phase architecture it is possible to gain 20 dB in blocking effect rejection in comparison to the classical IQ architecture.

Comparison of 24 GHz receiver front-ends using active and passive mixers in CMOS

This study compares the key parameters of two integrated receiver front-end architectures: low noise amplifier (LNA) with active mixer against LNA with passive mixer. The authors discuss the differences in the performance and their impact on system characteristics for radar applications. A low-IF down-conversion receiver implementation is considered. The results are compared in measurement for two 24 GHz receiver front-end chips realised in a 0.13 mum digital CMOS process. Both circuits have been characterised over automotive temperature range -40 to 125degC. The front-end with an active mixer offers lower LO power dependence and exhibits better temperature stability, whereas the front-end with a passive mixer has the advantage of better input-referred linearity and lower flicker noise.

Extension of an absolute vector error correction technique to wideband, high-frequency measurements

The authors have previously demonstrated how a transmitter (Tx), a reciprocal transmitter/receiver (Tx/Rx) signal path and two unidirectional receiver (Rx) paths can be used together with short, open and load standards for the absolute vector error correction (AVEC) of a Tx/Rx module. Once calibrated, this Tx/Rx module can then provide accurate vector measurements of the signals that are flowing into and/or out of the test port. In order to simplify the analysis, the AVEC technique was applied to a simplified baseband circuit that did not include frequency conversion mixers in a previous paper. Now, in this paper the authors first show how the AVEC technique can be extended to the vector calibration of high-frequency receivers that involve frequency conversion mixers. The authors then show how to calibrate a system that allows for wideband absolute phase relationship measurements of periodic modulated signals, provided that the same local oscillator is employed for the two down-conversion receivers, and different radio frequencies and intermediate frequencies are employed in these receivers. This novel AVEC technique is one of the key concepts in the design of a wideband absolute vector signal measurement system, which overcomes the limitations of traditional measurement instruments by combining the features of vector signal analysers, spectrum analysers and vector network analysers.

DE-INTERLEAVED SUBSAMPLING ARCHITECTURE FOR HOMODYNE RECEIVERS

This paper presents a de-interleaved subsampling receiver architecture suitable for homodyne receivers. The proposed topology requires only a single branch to down-convert and extract the in- phase (I) and quadrature (Q) baseband signals. Using a single- branch receiver eliminates the I=Q mismatch issue of traditional direct down-conversion receivers. The simplicity of the proposed receiver architecture makes it an alternative solution for multi-band and multi- standard applications.

Recursive Receiver Down-Converters With Multiband Feedback and Gain-Reuse

Receiver down-converter topologies are presented that provide simultaneous frequency conversion and baseband amplification within a mixer, in order to reduce power dissipation for a given dynamic range. The down-converted IF output of a mixer is reapplied to its input stage in a recursive manner, which significantly enhances the conversion gain, with current requirement determined primarily by the input transconductor of the mixer. Two down-converter topologies based on this technique are presented. One topology utilizes common-source NMOS devices as the RF input stage of the mixer, and reuses their transconductance for providing baseband gain. The second topology utilizes differential pairs as the RF input stage, and employs the transconductance of the tail current-source devices for baseband gain. The designs are implemented in a 0.13 mum CMOS technology and achieve peak conversion gains of 50 dB and 56 dB, with single side-band noise figures of 12.7 dB and 9.4 dB, and OIP3 values of 8 and 11 , respectively. They operate at a nominal supply of 1.2 V with bias current of 2.9 mA and 2.1 mA, respectively. The active die area is less than 0.1 mm for each design. Noise and linearity performance of the down-converters is analyzed, and the potential for enhancement of IIP3 through cancellation of nonlinear products is discussed.

Experimental Study of Jitter Effect on Digital Downconversion Receiver with Undersampling Scheme

Undersampling (or bandpass sampling) phase modulated signals directly at high frequency band, the harmful effects of the aperture jitter characteristics of ADCs (Analog-to-Digital converters) and sampling clock instability of the system can not be ignored. In communication systems the sampling jitter brings additional phase noise to the constellation pattern besides thermal noise, thus the BER (bit error rate) performance will be degraded. This paper examines the relationship between the input frequency to ADC and the sampling jitter in digital IF (Intermediate Frequency) downconversion receivers with undersampling scheme. This paper presents the measurement results with a real hardware prototype system as well as the computer simulation results with a theoretically modeled IF sampling receiver. We evaluated EVM (Error Vector Magnitude) in various clock jitter configurations with commonly used and reasonable cost ADCs of which sampling rates was 40 MHz. According to the results, the IF input frequencies of QPSK (16 QAM) signals were limited below around 290 (210) MHz for wireless LAN standard, and 730 (450) MHz for W-CDMA standard, respectively, in our best configuration.