Double-throw Switch Research Articles

Design and simulation of a smart master switch system based on multi-input XOR logic gate

Mechanical switches have been the conventional way of controlling electrical energy in different electrical systems such as: lighting systems, socket systems, and circuit breakers, especially in domestic, hospital, and industrial applications. Mechanical switches often require physical access to control different electrical devices that are connected to the power sources. The work presented in this paper aimed at designing and simulating a multi-input based Exclusive-Or master switch system that remotely controls the lighting and socket systems using the wireless switching mechanisms of Global System for Mobile communication and Bluetooth. The system therefore limits physical interaction that require use of the single pole double throw and keypad mechanical switches that are however included to act as fall-back mechanism in control of electrical devices. Within the recommended electrical safety measures, the design can be streamlined and integrated to remotely control lighting systems and sockets alongside the conventional mechanical switches in the consumer control unit.

Multifunctional Quad-Channel Diplexer-Integrated Single-Pole Double-Throw Switch With Three Operating Modes

Multifunctional Quad-Channel Diplexer-Integrated Single-Pole Double-Throw Switch With Three Operating Modes

Design and Analysis of K-Band Single-Pole Double-Throw Switches Based on GaAs Technology

Two K-band switch circuits, each consisting of a single-pole double-throw (SPDT) switch, have been built using a 0.15 μm GaAs process. One circuit utilizes diode techniques while the other utilizes field effect transistor (FET) techniques. The diode single-pole double-throw switches that have been devised exhibit exceptional linearity and are capable of withstanding high power levels. The switches exhibit a return loss of 10 dB or higher, an insertion loss of 3 dB or lower, and operate within a frequency range of 19 GHz to 25 GHz. They have a compact design with a core size of only 1.05 mm2 and consume a total power of 136.8 mW. The FET SPDT switch circuits are created utilizing a parallel–parallel quarter-wavelength transmission line architecture. This design allows for a higher power output compared to using a diode. The transistorized single-pole double-throw switch circuit is designed using a parallel–parallel quarter-wavelength transmission line architecture. This design ensures a low insertion loss. By adjusting the length of the transmission line, the circuit can operate in both frequency bands; the K-band and Ka-band.

X‐band high isolation single pole double throw switch based on resonant concept

AbstractUtilizing the 0.25 μm GaN HEMT process, a high‐isolation single pole double throw (SPDT) RF switch has been meticulously designed for the X‐band. The circuit topology employs a series‐shunt configuration to prevent signal leakage, thereby enhancing chip isolation. By incorporating series transistors and shunt inductors, LC resonance is achieved, significantly boosting isolation performance. To optimize port matching and ensure both heightened isolation and minimized insertion loss, inductors are strategically integrated into each port. The inclusion of these lumped inductors contributes significantly to reducing the chip's footprint. Die measurement results demonstrate that across the 8–12 GHz frequency spectrum, insertion loss remains below 1.1 dB, with isolation exceeding 36 dB. Remarkably, at 10.5 GHz, isolation peaks at an impressive 52 dB. Moreover, return loss surpasses 12 dB, and the 0.1 dB compression point input power stands at 43.5 dBm, all achieved within a compact chip area of only 1 mm2.

Design of class f reconfigurable power amplifiers

With the rapid development of mobile communication technology, RF amplifier requirements becoming higher, miniaturization, high efficiency and multi-band have gradually become a research hotspot. Based on these hot research directions, this paper designs a dual-band reconfigurable power amplifier. The input of the amplifier adopts a stepped impedance matching network, which has a good matching effect in the 1.6 - 2.8 GHz band. The output is switched by a single-knife double-throw switch to the corresponding band output matching network to achieve the fast switching of different frequency bands. The RF amplifier tube is designed by using Cree’s GaN chip CGH40010F, which has an additional power efficiency of more than 60% in the frequency range of 1.7 - 1.9 GHz and 2.5 - 2.7 GHz bands, a gain of about 12 - 14 dB and a saturated output power of more than 40 dBm. This design has the features of high efficiency, high gain, miniaturization and multi-band, which is applicable to the mobile communication system.

A 28 GHz GaN 6-Bit Phase Shifter MMIC with Continuous Tuning Calibration Technique.

A 28 GHz digitally controlled 6-bit phase shifter with a precision calibration technique in GaN high-electron mobility transistor (HEMT) technology is presented for Ka-band phased-array systems and applications. It comprises six stages, in which stages 1 and 2 for 5.625° and 11.25° are designed in the form of a switched-line circuit, and stages 3, 4, and 5 for 22.5°, 45°, and 90° are designed in the form of a switched-filter circuit. The final stage 6 for 180° is designed in a single-to-differential balun followed by a single-pole double-throw (SPDT) switch for achieving an efficient phase inversion. A novel continuous tuning calibration technique is proposed to improve the phase accuracy. It controls the gate bias voltage of off-state HEMTs at the stage 6 SPDT switch for fine calibration of the output phase. Fabricated in a 0.15 μm GaN HEMT process using a die size of 1.75 mm2, the circuit produces 64 phase states at 28 GHz with a 5.625° step. The experimental results show that the Root-Mean-Square (RMS) phase error is significantly improved from 8.56° before calibration to 1.08° after calibration. It is also found that the calibration does not induce significant changes for other performances such as the insertion loss, RMS amplitude error, and input-referred P1dB. This work successfully demonstrates that the GaN technology can be applied to millimeter-wave high-power phased-array transceiver systems.

Design and Characterization of W-Band Silicon Micromachined High-Power and High-Speed Photoconductive Evanescent-Mode Waveguide Single and Double Throw Switches

Design and Characterization of <i>W</i>-Band Silicon Micromachined High-Power and High-Speed Photoconductive Evanescent-Mode Waveguide Single and Double Throw Switches

Flexible Design Method for Multifunctional Filtering Diplexers Integrated With Single-Pole Double-Throw Switches

Flexible Design Method for Multifunctional Filtering Diplexers Integrated With Single-Pole Double-Throw Switches

Non-Contact Adaptive Voltage Sensor Based on Electric Field Coupling Principle.

Non-contact voltage sensors based on the principle of electric field coupling have the advantages of simple loading and unloading, high construction safety, and the fact that they are not affected by line insulation. They can accurately measure line voltage without the need to connect to the measured object. Starting from the principle of non-contact voltage measurement, this article abstracts a non-contact voltage measurement model into the principle of capacitive voltage sharing and deduces its transfer relationship. Secondly, it is theoretically inferred that the edge effect of the traditional symmetric structure sensor plate will cause the actual capacitance value between the sensor plates to be greater than the theoretically calculated capacitance value, resulting in a certain measurement error. Therefore, the addition of an equipotential ring structure is proposed to eliminate the edge additional capacitance caused by the edge effect in order to design the sensor structure. In addition, due to the influence of sensor volume, material dielectric constant, and other factors, the capacitance value of the sensor itself is only at pF level, resulting in poor low-frequency performance and imbuing the sensor with a low voltage division ratio. In this regard, this article analyzes the measurement principle of non-contact voltage sensors. By paralleling ceramic capacitors between the two electrode plates of the sensor, the capacitance of the sensor itself is effectively increased, improving the low-frequency performance of the sensor while also increasing the sensor's voltage division ratio. In addition, by introducing a single pole double throw switch to switch parallel capacitors with different capacitance values, the sensor can have different voltage division ratios in different measurement scenarios, giving it a certain degree of adaptability. The final sensor prototype was made, and a high and low voltage experimental platform was built to test the sensor performance. The experimental results showed that the sensor has good linearity and high measurement accuracy, with a ratio error of within ±3%.

Design and Analysis of Complementary Metal–Oxide–Semiconductor Single-Pole Double-Throw Switches for 28 GHz 5G New Radio

We propose a single-pole double-throw (SPDT) switch with low insertion loss (IL), high isolation, and high linearity for a 28 GHz 5G new radio. The transmit (TX) path is a π-network consisting of a parallel dynamic-threshold metal–oxide–semiconductor (DTMOS) transistor, M1, with large body-floating resistance, RB (DTMOS-R M1), a series one-eighth-wavelength (λ/8) transmission line (TL), and a parallel capacitance, Cant. The series λ/8-TL in conjunction with the parallel Cant and transistors’ capacitance constitute an equivalent λ/4-TL with a characteristic impedance of 50 Ω. This leads to low IL in the TX mode and decent isolation in the receive (RX) mode. The RX path is an L-network constituting a series impedance (of parallel inductance L1 and DTMOS-R M2) and a parallel DTMOS-R M3. This leads to a decent IL in the RX mode and isolation in the TX mode. The first SPDT switch (SPDT SW1) is designed and implemented in a 90 nm complementary metal–oxide–semiconductor (CMOS) with a top metal thickness (TMT) of 3.4 μm. A comparative SPDT switch (SPDT SW2) in a 0.18 μm CMOS with a thinner TMT of 2.34 μm is also designed and implemented. In the TX mode, SPDT SW1 achieves a measured IL of 0.67 dB at 28 GHz and 0.58–1 dB for 17–34.9 GHz and a measured isolation of 44.3 dB at 28 GHz and 25.6–62.3 dB for 17–34.9 GHz, one of the best IL and isolation results ever reported for millimeter-wave CMOS SPDT switches. The measured input 1 dB compression point (P1dB) is 28.5 dBm at 28 GHz. Moreover, in the RX mode, SPDT SW1 attains a measured IL of 1.9 dB at 28 GHz and 1.83–2.1 dB for 25–38.3 GHz and an isolation of 25 dB at 28 GHz and 24.5–27 dB for 25–38.3 GHz. The measured P1dB is 24 dBm at 28 GHz.

A Sigma-Delta Modulator with Single-Pole Double-Throw Analog Switch

In this paper, a high precision and high energy efficiency discrete-time switching capacitive 3-order Sigma-Delta modulator (SDM) is proposed. The SDM is applied to portable electroencephalograms (EEG) because of its little energy and good performance. The energy efficiency levels of the current mainstream modulator systems are analyzed and compared, and the CIFF modulator architecture which is most conducive to realizing high energy efficiency is selected. The single-loop CIFF structure is selected to give consideration to the accuracy and stability of the circuit. The circuit is implemented in a hierarchical structure, and a single-pole double-throw (SPDT) analog switch is adopted to overcome the difficulty of opening conventional CMOS analog switches at low supply voltages and the increase in threshold voltage Vth of NMOS devices due to the base bias effect. The proposed discrete-time Sigma delta ADC modulator is designed with SMIC 0.18um CMOS technology and achieves an SNDR of 101.6dB under a 1.8V power supply voltage and a signal bandwidth of 2kHz. The power consumption is 520uW and the significant bit (ENOB) is 16.58 bits.

Dual-Band Single-Pole Double-Throw Filtering Switch Using Multimode Cavity Resonators

A dual-band single-pole double-throw (SPDT) filtering switch using hybrid microstrip-cavity structure is proposed in this paper. Two rectangular cavities act as the multimode resonators, and the cross-shaped microstrip lines (MLs) are adopted to feed them. Then two filtering channels are constructed, while only one channel is supposed to be turned on in each operating state. For this purpose, PIN diodes are integrated into the two output MLs to switch the two channels arbitrarily. The channel using reversely biased PIN diodes is turned on with dual-band filtering response. On the contrary, the other channel using forward biased PIN diodes is switched off with high OFF-state suppression and channel isolation. The measurements indicate a dual-band filtering response along with below 0.75 dB insertion loss in the switched-on channel. And 38 dB suppression as well as 33.3 dB channel isolation is obtained in the switched-off channel. Benefitting from the hybrid microstrip-cavity structure, the bandwidths of the two bands could be adjusted independently. And meanwhile the two multimode cavities are shared by the two channels to compact the size. In this way, the proposed microstrip-cavity structure possesses a dual-band SPDT filtering switch response, flexible passbands and miniaturization.

A Sub-GHz CMOS SPDT Antenna Switch Employing Linearity-Enhanced Biasing Strategy for Second-Order Harmonic Reduction

A CMOS single-pole double-throw (SPDT) antenna switch employing linearity-enhanced biasing strategy is proposed for the second-order harmonic (H2) reduction. It was implemented and demonstrated using a 0.28-lm thick-oxide MOSFET in 65-nm CMOS process. The NMOS transistor of the conventional antenna switch is replaced with the CMOS transistor composed of an NMOS and PMOS transistor in parallel to improve second-order harmonic distortion (HD2). The optimum channel width of an NMOS and PMOS transistor is chosen to achieve odd symmetry characteristic of I-V curve with respect to the drain-to-source voltage swing (VDS), and, as a result, enhance HD2 of the antenna switch. In addition, the linearity-enhanced biasing scheme is adopted to the PMOS transistor as a conventional negative biasing method of the NMOS transistor. This prevents the degradation of the power handling capability in adopting the PMOS transistor to the antenna switch. In the measurement, the proposed single-stack SPDT antenna switch shows an insertion loss of less than 0.6 dB and an isolation of greater than 38 dB from 100 MHz to 1 GHz with an input and output return loss of greater than 25 dB. Concerning for H2 and third-order harmonic (H3), it shows H2 of -65 dBm and H3 of -90 dBm at 150 MHz when a single-tone RF signal with a power of +5 dBm is applied. Compared to the conventional NMOS-based antenna switch, the proposed CMOS-based antenna switch improves HD2 by approximately 8 dB, 7 dB, and 1 dB at 150 MHz, 400 MHz, and 1 GHz, respectively, while maintaining the comparable insertion loss, isolation, and third-order harmonic distortion (HD3).

A High-Power and Broadband GaN SPDT MMIC Switch Using Gate-Optimized HEMTs

A high-power, broadband monolithic microwave integrated circuit (MMIC) single-pole double-throw (SPDT) switch is designed with gate-optimized high-electron-mobility transistors (HEMTs) using AlGaN/Gallium nitride (GaN) technology. The foot length of the gate is varied from 200 to 250 nm, and the head length is varied from 500 to 750 nm in the T-gate structure to optimize the radio frequency (RF) performance. The SPDT switch is designed in a series–shunt–shunt topology using gate topology as a design parameter. The switch has achieved an insertion loss better than 0.75 dB throughout the 3.5–13.5-GHz bandwidth. It can transmit 30-W output power at 0.1-dB compression point and handle 47.5-dBm input power at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\textrm{1\,dB}}$</tex-math> </inline-formula> . The isolation is above 25 dB, and the return loss is better than 11 dB. With its low insertion and high power-handling capacity in broadband, the SPDT switch shows state-of-the-art performance for high-power communication systems and radar applications.

Spiral-Resonator-Based Frequency Reconfigurable Antenna Design for Sub-6 GHz Applications

This paper presents a novel frequency reconfigurable antenna design for sub-6 GHz applications, featuring a unique combination of antenna elements and control mechanisms. The antenna is composed of an outer split-ring resonator loaded with an inner spiral resonator, which can be adjusted through the remote control of PIN diode or Single Pole Double Throw (SPDT) switches. The compact antenna, measuring 22 × 16 × 1.6 mm3, operates in broadband, or tri-band mode depending on the ON/OFF states of switches. The frequency reconfigurability is achieved using two BAR64−02V PIN diodes or two CG2415M6 SPDT switches acting as RF switches. SPDT switches are controlled remotely via Arduino unit. Additionally, the antenna demonstrates an omni-directional radiation pattern, making it suitable for wireless communication systems. Experimental results on an FR-4 substrate validate the numerical calculations, confirming the antenna’s performance and superiority over existing alternatives in terms of compactness, wide operating frequency range, and cost-effectiveness. The proposed design holds significant potential for applications in Wi-Fi (IEEE 802.11 a/n/ac), Bluetooth (5 GHz), ISM (5 GHz), 3G (UMTS), 4G (LTE), wireless backhaul (4G and 5G networks), WLAN (IEEE 802.11 a/n/ac/ax), 5G NR n1 band, and Wi-Fi access points due to its small size and easy control mechanism. The antenna can be integrated into various devices, including access points, gateways, smartphones, and IoT kits. This novel frequency reconfigurable antenna design presents a valuable contribution to the field, paving the way for further advancements in wireless communication systems.

Design of BPF-Integrated SPDT Switch Based on Slotline Resonators Loaded With Diodes

Slotline Stepped-impedance resonators (SIR) loaded with p-i-n diodes are used to develop bandpass filter (BPF) integrated switches in this brief. The loaded diodes are used to switch the resonant conditions of the short-ended slotline resonators. The equations for their resonant conditions under different loads at different locations are derived and discussed. With these derived equations, the switchable filters are designed and synthesized using the classical coupled-resonator filter theory. The design concept is demonstrated by a Cascaded Quadruplet (CQ) BPFintegrated single-pole single-throw (SPST) switch at center frequency f0 = 1 GHz with with 47.7 dB OFF-state suppression (OSS). Finally, two compact BPF-integrated single-pole double-throw (SPDT) switches are designed and fabricated. One of them combines source-load (S-L) coupling and introduces two additional zeros outside the desired passband to improve the frequency selectivity. The other on fractal common feeding line is developed to reduce the impact of accumulated residual admittances from OFFstate channels, which shows high roll-off rate of sidebands as well as high port-to-port isolation of 53.1 dB, and its overall circuit size is only 0.051 λg2.

Measurement of Complex-Ratio Between Two RF Signals With Spectrum Analysis

A novel method to measure the amplitude-phase differences between two radio frequency (RF) signals is presented, based on spectrum analysis after periodic modulation. Two input signals are alternatively selected to enter the single-channel RF channel by a single-pole double-throw (SPDT) switch, which generates harmonics related to the channel unbalance. Amplitude-phase differences between two input signals can be obtained by analyzing the spectrum of received signal using discrete Fourier transform (DFT) in digital domain. Compared to conventional multichannel RF receivers, the proposed method has a concise structure and low-computational complexity. Simulation results are provided to verify its effectiveness over dynamic ranges of 60 dB and 360 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula> . A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L$</tex-math> </inline-formula> -band RF circuit is fabricated to measure the amplitude-phase differences over 35 dB and 360 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula> dynamic ranges. The measured results show good agreement to those by the vector network analyzer (VNA), certifying the effectiveness of proposed method.

A 28-GHz Four-Channel Beamforming Front-End IC With Dual-Vector Variable Gain Phase Shifters for 64-Element Phased Array Antenna Module

A 28-GHz fully differential four-channel beamforming front-end IC with variable gain phase shifters (VGPSs) is presented, of which orthogonal phase and gain control is achieved in a single block using the proposed dual-vector synthesis technique. This greatly reduces chip size, power consumption, and calibration complexity. The antenna switch embedded in the front-end matching network minimizes degradation of the transmitter (TX) efficiency and receiver (RX) noise figure. The multi-mode power amplifier (PA) with a built-in linearizer is presented to have high efficiency and linearity for all power modes, which reduces power consumption during gain control. Also, a differential four-way power divider and an single pole double throw (SPDT) switch are introduced in the common path, which has a small chip size and a low insertion loss. By adopting differential structures for all components in the four-channel IC, the effect of parasitic grounding inductances due to bonding and package is minimized. Thanks to the proposed dual-vector VGPS, the rms gain error of 0.21 dB and the peak phase variation of ±1.7° are achieved during phase control and gain control, respectively, without any calibration. The four-channel front-end IC also achieves rms phase error of only 1.4° during the simultaneous phase and gain control without any calibration. It has a TX OP1dB of 13.3 dBm and the highest linear output power of 7.2 dBm with 400-MHz 64-QAM fifth-generation (5G) new radio (NR) signals with 9.6-dB peak-to-average power ratio (PAPR). Also, this article presents a 64-element brick-type phased array antenna using four-channel core chips. It shows a high effective isotropic radiated power (EIRP) of 54.4 dBm at 28 GHz. An over-the-air link is demonstrated with a competitive data rate of 4 Gb/s using 64-QAM waveforms over all scan angles at a distance of 100 m.

A Dual-Component Electric Probe Embedded With a 0°/180° Hybrid Coupler for Near-Field Scanning

In this article, a Ka -band dual-component electric probe is proposed in low temperature co-fired ceramic for near-field scanning, which consists of a sensing part of two symmetric L-shaped strips and a 0°/180° hybrid coupler. The responses to the tangential and normal electric components are outputted to the difference and sum ports without post-processing, to avoid the errors due to phase measurements at high frequencies. A grounded coplanar waveguide (GCPW) is used as a standard kit. Equations are derived carefully to take the imperfect terminations into account. To further improve the sensitivity and measurement efficiency, a low noise amplifier (LNA) and an absorptive single pole double throw (SPDT) switch are integrated with the probe. Simulated and measured results indicate that the probe can characterize the near electric field distributions within the band of 27.2–30 GHz, and the sensitivity of the active probe prototype is improved by 17–18 dB at 28 GHz when compared with the passive one. The passive probe prototype is utilized to scan the near electric field of an integrated transmitting front-end module at 28.5 GHz.

A 60-GHz Variable-Gain Phase Shifter With an Active RL Poly-Phase Filter

A 60-GHz variable-gain phase shifter consisting of an active I/Q generator and Gilbert-cell-based summing amplifier fabricated in a 65-nm bulk CMOS process is presented here. The proposed I/Q signal generator is implemented by inserting an RL poly-phase filter into the interstage node of a cascode amplifier, which provides good interstage matching and results in a finite gain in the I/Q generator. It also provides good isolation characteristics between the I/Q generator and the subsequent vector-summing amplifier due to the common gate buffer stages. Therefore, it minimizes the rms gain and phase errors of the phase shifter by maintaining accurate I/Q signals regardless of the input impedance of the vector-summing amplifier, which varies with the gain and phase states. The vector-summing amplifier is operated by a current-steering digital to analog converter (DAC) to keep the total dc current constant regardless of the gain and phase states, which makes the output return loss constant. The DAC makes the vector-summing amplifier generate an arbitrary vector by determining the sizes of the I and Q vectors, and the double pole, double throw (DPDT) switch determines the quadrants. The rms gain and phase errors of the proposed variable-gain phase shifter show the values of 0.13 dB and 0.36°, respectively, at 60 GHz with 4-bit gain control in a 20-dB dynamic range and 5-bit phase control at 360°. In the 3-dB frequency range of 56.8–64.1 GHz, the rms gain and phase error outcomes are 0.26 dB and 1.44°, respectively. The chip area and overall power consumption are measured and found to be 0.55 mm2 and 14.52 mW, respectively.