Double-polysilicon Bipolar Transistors Research Articles

Time-Dependent Hot Carrier Degradation in Polysilicon Emitter Bipolar Transistors Under High Current and Radiation Combined Stress

A comparative combined stress-induced reliability issues between Auger hot carrier and ionizing radiation in double polysilicon bipolar transistor is investigated. The observed differences in the low-frequency noise spectra of devices with different stressing conditions could be interpreted as the differences in the defects-related noise contributions. Low-frequency noise and electrical performance degradation results show that Auger hot carriers greatly induce the atomic hydrogen depassivating the dangling bonds in grain boundaries of emitter polysilicon. However, ionizing radiation damage occurs both at SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interfaces and in the oxide layer. 1/f noise characteristics indicate that these two damages have different time dependences.

Comparison of low frequency noise and high frequency performances of double and simple polysilicon Bi-CMOS BJT

The issue of this paper concerns 0.35 μm Bi-CMOS double polysilicon bipolar transistors and 0.5 μm Bi-CMOS simple polysilicon bipolar transistors. Low-frequency noise measurements are performed. Noise spectral densities are analysed versus bias and geometry. From these noise measurements, base and emitter series resistances are extracted. A comparison of both technologies is done. Though double polysilicon transistors have a more complex structure than the simple polysilicon ones, they exhibit similar or even better performances. Indeed, DC characteristics and noise levels are equivalent for both technologies. Double polysilicon transistors exhibit a reduction of the base resistance and a significant improvement of the transition frequency f T is obtained.

Extraction of emitter and base series resistances of bipolar transistors from a single DC measurement

A new procedure for extracting the emitter and base series resistances of bipolar junction transistors is presented. The parameters are extracted from a single measurement in the forward active region on one transistor test structure with two separate base contacts, making it a simple and attractive tool for bipolar transistor characterization. The procedure comprises two methods for extracting the emitter resistance and two for extracting the base resistance. The choice of method is governed by the amount of current crowding or conductivity modulation present in the intrinsic base region. The new extraction procedure was successfully applied to transistors fabricated in an in-house double polysilicon bipolar transistor process and a commercial 0.8-/spl mu/m single polysilicon BiCMOS process. We found that the simulated and measured Gummel characteristics are in excellent agreement and the extracted series resistances agree well with those obtained by means of HF measurements. By adding external resistors to the emitter and base and then extracting the series resistances, we verified that the two base contact test structure offers a simple means of separating the influence of emitter and base series resistances on the transistor characteristics.

The effect of emitter overetch and base implantation tilt on the performance of double polysilicon bipolar transistors

In a self-aligned double polysilicon bipolar junction transistor (BJT) process, the emitter window is opened by etching through the base polysilicon. The etch always penetrates a certain depth (overetch depth) into the upper epitaxial layer of the silicon substrate. Experimental results, confirmed by process and device simulation, show that the cut-off frequency fT increases with overetch depth. According to the simulation, the increase in fT is a consequence of a shorter base width along the perimeter of the intrinsic base. The base shortening results from the weakened electrical link between the extrinsic and intrinsic base which in turn is caused by the emitter window overetch. It is found that the fT dependence upon overetch depth is stronger for 7° than for 0° wafer tilt during the intrinsic base ion implantation. During the implantation with a 7° tilt, the emitter window sidewalls lead to the formation of an even shorter base width along part of the perimeter of the intrinsic base. However, excessive emitter window overetch degrades the BJT performance in general, resulting in high collector leakage current, low emitter-to-collector breakdown voltage and low maximum oscillation frequency (fMAX). The simulation results also demonstrate that the effect of emitter overetch and base implantation tilt will be more severe when the BJT is scaled down to deep-submicron dimensions.

The influence on electrical performance of double-polysilicon bipolar transistors by forming gas annealing

The influence on the electrical performance of double-polysilicon self-aligned bipolar junction transistors by hydrogen passivation using forming gas annealing (FGA) was investigated. While the collector current remained essentially unaffected, the base current decreased substantially after the FGA. As a result, the peak DC current gain increased approximately by a factor of three. A simple model was employed to extract the base saturation current components. It was found that the base recombination currents mainly were related to the defects (i.e. recombination centers) located at the SiO2/monosilicon interface beneath the L-shaped emitter window spacers. The FGA also caused the peak cut-off frequency fT to increase by 40%. The fT enhancement is probably related to passivation of defects in the emitter/base space-charge region at the SiO2/monosilicon interface beneath the sidewall spacers.

Effects of buried layer geometry on characteristics of double polysilicon bipolar transistors

Dependences of electrical characteristics of double polysilicon transistors on n/sup +/ buried islands (subcollector) are examined. By simply modifying layouts of the buried island, the Early voltage (V/sub A/), collector-to-emitter breakdown voltage (BV/sub CEO/), and /spl beta//spl times/V/sub A/ product of transistors are increased from 42, 5.6, and 3070 V to 61, 6.7, and 3820 V, respectively, while the peak cutoff frequency at a V/sub CE/ of 1.5 V is decreased from around 21 to 17 GHz. Exploiting these results, it may be feasible to inexpensively integrate transistors with better f/sub T/-BV/sub CEO/ and f/sub T/-V/sub A/ tradeoffs for analog and power handling characteristics along with transistors optimized for high-speed operation. These results also indicate that the buried island geometry control could be an issue for controlling electrical characteristics for scaled bipolar transistors.

A new technique for forming a shallow link base in a double polysilicon bipolar transistor

A new technique is presented for forming a shallow link base in a double polysilicon bipolar transistor. This method is easily integrated into an advanced BiCMOS process, making use of a disposable polysilicon spacer technology for MOSFET LDD formation. This new scheme allows independent optimization of active and link base regions while providing improvements in base-emitter breakdown and resistance to bipolar hot carrier degradation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 /spl mu/m/sup 2/ with conventional I-line lithography and 7.32 /spl mu/m/sup 2/ with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 /spl mu/m active pitch, MOSFET transistors designed for a 0.80 /spl mu/m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance. >

On contact resistance measurement using four-terminal Kelvin structures in advanced double-polysilicon bipolar transistor processes

The contact between a polycrystalline silicon (polysilicon) layer and a silicon substrate is investigated for an advanced double-polysilicon bipolar transistor process. Contact resistances are measured using four-terminal cross bridge Kelvin structures. The specific contact resistivity of the interface and the sheet resistance of the doped substrate region directly underneath the contact are extracted using a two-dimensional simulation model originally developed for metal-semiconductor contacts. The extracted sheet resistance values are found to be larger than those measured using van der Pauw structures combined with anodic oxidation and oxide removal. During the fabrication of the contacts, epitaxial realignment of the polysilicon in accordance to the substrate orientation and severe interdiffusion of dopants across the interface take place, which complicate the characterization. The validity of the two-dimensional simulation model applied to the poly-mono silicon contact is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

X-ray lithography induced radiation damage in CMOS and bipolar devices

Radiation effects from a synchroton x-ray lithography source on the performance degradation and long term reliability of high performance self-aligned bipolar devices and deep sub-micron CMOS devices are studied. The hot-carrier properties of the x-ray induced damage in CMOS devices, such as interface states, positive oxide charges and neutral traps have been examined. The effect of these radiation induced defects and their impact on the DRAM circuits in terms of the performance and reliability are discussed. In the self-aligned, double polysilicon bipolar transistor structure interface states and trapped charges can be generated by the radiation source in the sidewall oxide near the emitter-base junction such damage can increase the emitter-base leakage current. This increase of base current can substantially degrade the device current gain at low bias.