The effect of emitter overetch and base implantation tilt on the performance of double polysilicon bipolar transistors

Abstract

In a self-aligned double polysilicon bipolar junction transistor (BJT) process, the emitter window is opened by etching through the base polysilicon. The etch always penetrates a certain depth (overetch depth) into the upper epitaxial layer of the silicon substrate. Experimental results, confirmed by process and device simulation, show that the cut-off frequency fT increases with overetch depth. According to the simulation, the increase in fT is a consequence of a shorter base width along the perimeter of the intrinsic base. The base shortening results from the weakened electrical link between the extrinsic and intrinsic base which in turn is caused by the emitter window overetch. It is found that the fT dependence upon overetch depth is stronger for 7° than for 0° wafer tilt during the intrinsic base ion implantation. During the implantation with a 7° tilt, the emitter window sidewalls lead to the formation of an even shorter base width along part of the perimeter of the intrinsic base. However, excessive emitter window overetch degrades the BJT performance in general, resulting in high collector leakage current, low emitter-to-collector breakdown voltage and low maximum oscillation frequency (fMAX). The simulation results also demonstrate that the effect of emitter overetch and base implantation tilt will be more severe when the BJT is scaled down to deep-submicron dimensions.