Double-metal CMOS Research Articles

Benchmarking of DPL-based 8b × 8b novel wave-pipelined multiplier

ABSTRACTThe present study examines double pass-transistor logic (DPL) and evaluates the performance of a proposed DPL-based 8b × 8b wave-pipelined pair-wise multiplier. It then compares some of its critical performance-parameters with a Normal-Process-Complementary-Pass-transistor-Logic (NPCPL) based design. Double transmission properties with balanced input capacitance of DPL gate, is the focus of the present work to improve multiplier performance like throughput and noise margin at reduced supply. In DPL both N-type and P-type devices help balanced transmission of logic ‘1’ and logic ‘0’ that in turn reduces data-dependent delay variation, and is therefore suitable for time equalised applications. Pulse-triggered TSPC (true single phase clocking) flip-flop (PTTFF) is once again used to design I/O registers of the multiplier for the advantages already stated in the previous work. The design is optimised and validated on TSMC-0.18 µm single-poly double-metal (SPDM) CMOS technology at 25°C temperature. Parameters for comparison include power-dissipation, throughput, latency, area and noise-margin under 2 V, 1.8 V and 1.5 V supply.

Label-Free CMOS Bio Sensor With On-Chip Noise Reduction Scheme for Real-Time Quantitative Monitoring of Biomolecules

We present a label-free CMOS field-effect transistor sensing array to detect the surface potential change affected by the negative charge in DNA molecules for real-time monitoring and quantification. The proposed CMOS bio sensor includes a new sensing pixel architecture implemented with correlated double sampling for reducing offset fixed pattern noise and 1/f noise of the sensing devices. We incorporated non-surface binding detection which allows real-time continuous monitoring of DNA concentrations without immobilizing them on the sensing surface. Various concentrations of 19-bp oligonucleotides solution can be discriminated using the prototype device fabricated in 1- μm double-poly double-metal standard CMOS process. The detection limit was measured as 1.1 ng/μl with a dynamic range of 40 dB and the transient response time was measured less than 20 seconds.

Extracción de parámetros eléctricos de inversores CMOS de compuerta flotante

This work provides an accurate methodology for extracting the floating-gate gain factor g, of CMOS floating-gate inverters with a clock-driven switch for accessing temporarilly to the floating-gate. With the methodology proposed in this paper, the g factor and other parasiticcapacitances coupled to the floating-gate can be easily extracted in a mismatch-free approach. This parameter plays animportant role in modern analog and mixed-signal CMOS circuits, since it limits the circuit performance. Theoretical and measured values using two test cells, fabricated in a standard double poly double metal CMOS AMI-ABN process with 1.2mm design rules, were compared. The extracted parameters can be incorporated into floating-gate PS pice macromodels for obtaining accurate electrical simulation.

The influence of hard-baking temperature applied for SU8 sensor layer on the sensitivity of capacitive chemical sensor

SU8, the near-UV photosensitive epoxy-based polymer was used as a sensor layer in the capacitive chemical sensor, ready for integration with a generic double-metal CMOS technology. It was observed that the response of the sensor slowly increases with the temperature applied in hard-baking process as long as it remains below 300°C. At this temperature the response of the sensor abruptly increases and becomes almost threefold. It was shown that fully crosslinked structure of the sensor layer becomes opened and disordered when the sensor is hard-baked at temperatures between 300°C and 320°C, that is, still well below the degradation temperature of the polymer. These changes in chemical structure were analyzed by Fourier-transform infrared spectroscopy. The temperature-dependent changes of the sensor layer structure enable one to prepare a combination of capacitive chemical sensors with good discrimination between some volatile organic compounds.

Eight-Bit Semiflash A/D Converter

An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are evaluated by the same array of comparators. The auto-zeroed comparators also perform the function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result, a moderate conversion speed has been combined with a drastically reduced power consumption. The ADC was fabricated in a standard 0.6 μm double-poly, double-metal CMOS process. Experimental results show monotonic conversion with very low integral and differential nonlinearities. These features, combined with the ultra-low power consumption, make the proposed circuit very suitable for low-power mixed-signal applications.

Integrated Hall Microsystem with Current Re-Use

A new architecture of a Hall microsystem for low-power applications is presented. The innovation in this paper lies in the re-use of the electric current for biasing of several parts in the microsystem permitting substantial reduction of the current consumption. In this manner, four Hall devices were embedded into a differential difference amplifier, and signal treatment techniques for 1/f noise suppression were implemented to the system. The microsystem integrated in a standard 0.8 um double-poly, double-metal CMOS process exhibits an output sensitivity of 37.5 V/T and a magnetic field resolution of 500 nT/√Hz at 1 Hz. Its current consumption was reduced by 45% down to 2.4 mA compared to a similar Hall microsystem with conventional architecture having separated biasing of the sensing part and the electronic part.

A 1.48-mW Low-Phase-Noise Analog Frequency Modulator for Wireless Biotelemetry

This paper presents a low-phase-noise, hybrid LC-tank, analog frequency modulator for wireless biotelemetry employing on-chip NMOS varactors in the inversion region as the frequency tuning element. We demonstrate that a correct estimate for the destination signal-to-noise ratio, which quantifies the quality of the wirelessly received signal in a frequency-modulated biotelemetry system, is only achieved after taking into account the large-signal oscillation effect on the tank varactor. A prototype chip is fabricated using AMI 1.5-microm double-poly double-metal n-well CMOS process, and exhibits a measured gain factor of 1.21 MHz/V in the mid-range of the tuning voltage and a phase noise of -88.6 dBc/Hz at 10-kHz offset from the 95.1-MHz carrier while dissipating 1.48 mW from a 3 V power supply leading to a figure of merit (FOM) of -166.5 dBc/Hz. The VCO is successfully interfaced with a penetrating silicon microelectrode with 700 microm2 iridium recording sites for wireless in vitro recording of a 50 Hz simulated normal sinus rhythm signal from saline over a distance of approximately 0.25 m. Given a typical gain of approximately 40 dB for fully integrated front-end bioamplifiers, a wireless recording microsystem employing this VCO would be capable of detecting input biopotentials down to the submilivolt range.

A Low Voltage Wide-Input-Range Bulk-Input CMOS OTA

The Gm-C technique is extensively used for continuous-time filtering applications because it results in tunable, wideband and compact designs. In this paper, an OTA architecture using a novel bulk-input differential pair without the use of a tail current source is proposed. Good CMRR is still achieved by using the gate terminal to control the total current in the differential pair, via the use of a dummy pair. The OTA also exhibits a wide differential input range and good Gm-tunability. For this design, two standard double-poly double-metal CMOS processes were investigated: a 0.8 ?m process having a nominal threshold voltage of around 0.7 V and a 0.35 ?m process having a nominal threshold voltage of 0.5 V. Simulation results are presented for both designs while test results are presented, for the OTA, implemented using the 0.8 ? m process, used in a second order cochlea low-pass filter.

A 3.9-/spl mu/m pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel

A 3.9-/spl mu/m pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel has been developed for mobile applications. The newly developed CMOS pixel architecture realizes the minimum number of the transistors in one pixel. Small pixel size and sufficient fill factor are achieved by using the shared pixel architecture and floating diffusion driving. High conversion gain, low random noise, and low dark current are achieved by buried photodiode with complete charge transfer capability and correlated double sampling (CDS) circuit. The image sensor is fabricated in a thin planarized 0.35-/spl mu/m single poly-Si double-metal customized CMOS process in order to provide good image performance. The image sensor achieves low noise floor of 330 /spl mu/V and low dark current of 50 pA/cm/sup 2/ at 45/spl deg/C. This image sensor also realized various functions by on-chip digital and analog circuits.

Analog CMOS Chipset for a 2-D Sound Localization System

2-D sound localization can be carried out by extracting a number of features, known as localization cues, from two received left and right signals. This paper presents the measurement results obtained from three cue extraction chips implemented using standard 0.8 μm double-poly double-metal CMOS technology (threshold voltage: 0.8 V) and operating at a supply voltage of ±0.9 V. The chips consist of an onset detector which determines those portions of the received waveform which contain primarily incident (as opposed to echo) information, a spectral cue front-end and a time delay estimator used for the extraction of spectral cues and time delay cues, respectively. Some test results from each chip are first presented, together with measured cue values. The response of the complete system, with different source locations and under different noise and input signal conditions is then investigated. Results show that 2-D localization accuracy of 5° is possible using hardware-extracted localization cues. The performance of the onset detector in reducing errors arising from echo interference is also assessed. Finally, the localization performance of the system using different sound sources is presented. To our knowledge, these are the first test results obtained from such an analog hardware for a 2-D sound localization system.

High Speed Curve Interpolating D/A Converter

This paper presents a design of high speed curve interpolating D/A converter. We improve 8-bit data to 12-bit data, so the data resolution increases 16 times than that of original 8-bit data. The curve interpolator is developed from the linear interpolator. The simulation speed curve interpolator is about 500 MHz. The chip is fabricated by 0.8 μm double-metal single poly CMOS technology. The active interpolation size of chip is 1 × 1 mm2. The power dissipation is 200 mWatts at 5volt and 500 MHz for simulation result and 80 mWatts at 5 volt and 50 MHz for measurement result. The errors of interpolating result of curve interpolators are about 20 times less than that of original signal.

A Fully Integrated Neural Recording Amplifier With DC Input Stabilization

This paper presents a low-power low-noise fully integrated bandpass operational amplifier for a variety of biomedical neural recording applications. A standard two-stage CMOS amplifier in a closed-loop resistive feedback configuration provides a stable ac gain of 39.3 dB at 1 kHz. A subthreshold PMOS input transistor is utilized to clamp the large and random dc open circuit potentials that normally exist at the electrode-electrolyte interface. The low cutoff frequency of the amplifier is programmable up to 50 Hz, while its high cutoff frequency is measured to be 9.1 kHz. The tolerable dc input range is measured to be at least +/- 0.25 V with a dc rejection factor of at least 29 dB. The amplifier occupies 0.107 mm2 in die area, and dissipates 115 microW from a 3 V power supply. The total measured input-referred noise voltage in the frequency range of 0.1-10 kHz is 7.8 microVrms. It is fabricated using AMI 1.5 microm double-poly double-metal n-well CMOS process. This paper presents full characterization of the dc, ac, and noise performance of this amplifier through in vitro measurements in saline using two different neural recording electrodes.

Micro-Power Low-Offset Instrumentation Amplifier IC Design for Biomedical System Applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.

Pulse width control loop as a duty cycle corrector

The clock distribution and generation circuitry forms a critical component of current synchronous digital systems. A digital system?s clocks must have not only low jitter, low skew, but also well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital [8]. In this paper, we propose a pulse width control loop referred as MPWCL (modified pulse width control loop) that adopts the same architecture as the conventional PWCL, but with a new pulse generator and new charge pump circuit as a constituent of the duty cycle detector. Thanks to using new building blocks the proposed pulse width control loop can control the duty cycle in a wide range, and what is more important it becomes operative in saturation region too, what provides conditional for fast locking time. For 1.2 ?m double-metal double-poly CMOS process with Vdd = 5 V and operating frequency of 133 MHz, results of SPICE simulation show that the duty cycle can be well controlled in the range from 20 % up to 80 % if the loop parameters are properly chosen.

Voltage controlled delay line for digital signal

This paper describes dual delay locked loop architecture with a mixed mode phase tuning method. The circuit accomplishes low jitter, unlimited phase shift in a large operating range, and accurate phase alignment with high resolution for relatively low input clock frequency. The architecture employs two DLL loops. The first one is digital and is used for generating coarsely spaced clock pulses, while the second is analog and is intended for accurate and precise fine phase shifting. Simulations show that this circuit has 2?r radians phase shift capability, and can resolve 25ps phase error at input clock frequency of 1MHz, using 1.2^m double-metal double-poly CMOS technology.

Microelectronic Bonding Processes Monitored by Integrated Sensors

AbstractReal‐time monitoring methods are beneficial for the control, optimization, and failure analysis of microelectronic packaging processes. The focus of this chapter is on the real‐time monitoring of two widely used processes, soft solder die bonding and thermosonic ball bonding. The methods presented here use uniquely developed microsensors integrated on custom‐made test chips using commercial double‐metal CMOS processes.For the soft solder die bonding process, nine aluminum‐based resistive temperature detectors were integrated on various locations on a test chip. The temperature was monitored during the placement of the test chip on the leadframe. The experimental results describe the wetting and spreading effects of the molten solder under the drip. Together with numerical results obtained with a transient thermal finite element model, the beginning of wetting can be quantified. For the soft solder PbSn10, wetting occurred around 30 ms after touch down. This method hence can be used to determine wetting times under different process conditions. The wetting time determines an upper limit of the through put of the process.For the thermosonic ball bonding process, temperature and force sensors were integrated on test chips. The sensors are aluminum resistors and piezoresistive p+‐ and n+‐diffused resistors placed around bond pads. A bond quality parameter can be derived from the temperature signal variation during bonding. The piezoresistive sensors permit the measurement of forces in the x‐, y‐, and z‐directions simultaneously. The ultrasonic tangential force signal reached a typical value of 0.12 N on a 50μm diameter contact zone and revealed significant process characteristics. Four process phases are identified which are necessary for a successful ball bond formation. These phases are assigned to initial stiction, sliding, bond growth, and deformation effects.

An HDR CMOS image sensor with spiking pixels, pixel-level ADC, and linear characteristics

A high dynamic range (HDR) CMOS image sensor architecture based on spiking pixel cells and its first implementation, a linear 128-pixel sensor, is presented. The pulse rate of the pixel cell is proportional to the local light intensity. The pixel cell features a pixel-level analog-to-digital (A/D) conversion by pulse counting. It allows one to tradeoff conversion precision versus frame rate. Sample sensor chips have been manufactured using a 0.8-/spl mu/m double metal CMOS technology, and the test results confirming the feasibility of the chosen approach are reported.

Pipeline direct digital frequency synthesiser using decomposition method

A direct digital frequency synthesiser using a new decomposition method without the large sine ROM table is presented. To improve its operating frequency a pipeline structure has been utilised. It has been fabricated in a 0.6 µm single-poly double-metal (SPDM) CMOS process and its core area is 0.95 × 1.1 mm2. The maximum operating frequency is 85 MHz. For a 10 MHz sinusoidal output, the phase noise is –114 dBc/Hz at an offset frequency of 10 kHz. The measured SNR is 60.77 dB and worst case spurious is –67.6 dBc. Its power dissipation is 80 mW at 80 MHz under the 5 V supply.

Differential-voltage attenuator based on floating-gate MOS transistors and its applications

In this brief, a very simple differential voltage attenuator based on floating-gate MOS transistors (FGMOS) is proposed. The attenuator constructed by only two stacked identical FGMOS in saturation region, provides a voltage output proportional to the difference of the two input voltages. The advantages of this attenuator are the low supply operation, the rail-to-rail input range with small linearity error and the single-ended input processing. A very efficient technique to transform any circuit that requires only balanced inputs into the single-ended counterpart based on the attenuator, is proposed. Using this technique, a number of single-ended computational circuits are produced such as voltage squarer, four-quadrant multiplier, and vector summation circuit. The circuits can be fabricated in standard double-poly, double-metal CMOS technology and they are suitable for analogue signal processing and neural networks applications. SPICE simulation results using 2-/spl mu/m MIETEC CMOS process parameters demonstrate the feasibility and the accuracy of the circuits.

A 1 V second order Sigma-Delta modulator

A second order switched capacitor sigma-delta modulator operating at a supply voltage of 1 V is presented. This low supply voltage restricts the gate overdrive voltage available for switching transistors. The design relies on the elimination of critical switches by using a modified switched op amp for the integrator and novel switched half-supply and reference voltage generators. The design has been carried out in a fully differential configuration in order to minimize errors arising from charge injection and clock-feedthrough effects. The converter has been implemented using a conventional 0.8 μm double-poly double-metal CMOS process, having a nominal threshold voltage of 0.75 V. Test results, showing more than 9 bits of resolution with an oversampling ratio of 64, are also presented.