Abstract
A direct digital frequency synthesiser using a new decomposition method without the large sine ROM table is presented. To improve its operating frequency a pipeline structure has been utilised. It has been fabricated in a 0.6 µm single-poly double-metal (SPDM) CMOS process and its core area is 0.95 × 1.1 mm2. The maximum operating frequency is 85 MHz. For a 10 MHz sinusoidal output, the phase noise is –114 dBc/Hz at an offset frequency of 10 kHz. The measured SNR is 60.77 dB and worst case spurious is –67.6 dBc. Its power dissipation is 80 mW at 80 MHz under the 5 V supply.
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