Double-metal CMOS Technology Research Articles

Combined digital zooming and digital effects system utilizing CCD signal characteristics

An image processing system for digital zooming and digital effects is proposed. This system directly processes the CCD (charge coupled device) signal without separating it into luminance and chrominance signals, based on the characteristics of the color filter array in the CCD. By using the proposed color signal processing method, and efficient and high-quality digital zooming system is obtained. Various special effect functions are included in the system by adding simple controls for the addresses of the accompanied image buffers. The digital zooming can magnify the real-time dynamic images up to 4 times by 25 discrete steps. The digital effects unit achieves various visual effects by controlling the accompanied image buffers. To realize the proposed system, approximately 270000 transistors are integrated in a single chip VLSI by using 0.8 mu m double metal CMOS technology. >

An area-efficient median filtering IC for image/video applications

An area-efficient IC for high-throughput median filtering applications is presented. This IC implements a modified delete-and-insert sorting algorithm which is very efficient for running order statistics applications. In hardware design, the algorithm is first mapped onto a mapped onto a regular PE (processing element) structure, where each PE consists of shift register, comparator, and some control gates. Then, full-custom circuit/layout design of the PE is conducted to meet the performance requirement. A prototype chip for 64 input samples is implemented and tested. Results show that a clock rate of up to 50 MHz can be achieved using a 1.2 mu m CMOS double-metal technology. Two outstanding features of this IC are: any specified order of input pattern can be produced within one clock cycle and each chip can handle at most 64 data and can be cascaded as the number of sorted data is over 64. Thus, this resolved the bottleneck of median search in hardware realization for many system designs, making real-time performance achievable. >

Associative IC memories with relational search and nearest-match capabilities

The authors present the design and implementation of content addressable memories (CAMs) that execute relational and nearest-match instructions. Implementation of a novel relational search cell is presented. Direct performance comparison shows an order-of-magnitude improvement over existing designs with similar cell area. The design and implementation of a neural-inspired nearest-match CAM using a winner-take-all (WTA) network is presented. An original approach to analyzing such neural-inspired CAMs is presented. A model which describes the behavior of the WTA network is derived to be utilized in the design and performance prediction of the network. Performance of the WTA network in differentiating between words with large bit mismatches is analyzed, and an upper bound is set. Fully functional prototype chips have been fabricated through MOSIS using 2- mu m double-metal CMOS technology. Theoretical, simulation, and physical chip measurements are in good agreement.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 100-MHz 2-D discrete cosine transform core processor

A 100-MHz two-dimensional discrete cosine transform (DCT) core processor applicable to the real-time processing of HDTV signals is described. An excellent architecture utilizing a fast DCT algorithm and multiplier accumulators based on distributed arithmetic have contributed to reducing the hardware amount and to enhancing the speed performance. A layout scheme with a column-interleaved memory and a new ROM circuit are introduced for the efficient implementation of memory-based signal processing circuits. Furthermore, mean values of errors generated in the core were minimized to enhance the computational accuracy with the word-length constraints. Consequently, it features the fastest operating speed and the smallest area with sufficient accuracy to satisfy the specifications in CCITT recommendation H.261. The core integrates about 102 K transistors and occupies 21 mm/sup 2/ using 0.8- mu m double-metal CMOS technology. >

A 3.3-V 12-ns 16-Mb CMOS SRAM

The authors describe a 16 Mbit (2 M*8) SRAM with a 12-ns access time using a 0.4- mu m quadruple-polysilicon, double-metal CMOS technology with TFT (thin-film transistor) load memory cells. An access time of 12 ns is obtained with an optimized rotated memory cell array layout and a read bus midlevel voltage preset scheme (RBMIPS). An on-chip test circuit is included for efficient testing. The test circuit has three modes: redundant rows test, redundant columns test, and 16-bit parallel test. >

Image segmentation on a 2D array by a directed split and merge procedure

A 2D array implementation of image segmentation by a directed split and merge procedure is proposed. Parallelism is realized on two levels: one within the split and merge operations, where more than one merge (or split) may proceed concurrently, and the second between the split and merge operations, where several splits may be performed in parallel with merges. Both the split and merge operations are based on nearest neighbor communications between the processing elements (PEs), and facilitating low communication costs. The basic arithmetic operations required to perform split and merge are comparison and addition, allowing a simple structure of the PE as well as a hardwired control. A local of 512 bytes is sufficient to hold the interim data associated with each PE. A prototype PE has been constructed using 3 mu m double-metal CMOS technology. Scaling up to 0.8 mu m, it is possible to incorporate 32 PEs on a 5 cm/sup 2/ chip. With sufficiently large PE window sizes, image segmentation can be achieved in linear time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Associative memory integrated circuit based on neural mutual inhibition

Hardware associative or content-addressable memory (CAM) which finds in one operation the nearest match to input data among several templates is very crucial in the design of effective pattern recognition systems. We call this type of memory a relaxative CAM (RCAM) as opposed to the traditional exact-match CAM design. A compact implementation of an RCAM calls for the employment of a neural network model. In the paper we present the design and silicon implementation of an RCAM using a neural mutual inhibition network as the relaxation circuit. Spice simulations of the mutual inhibition and the RCAM performance are presented. A 16-word 12-bit IC has been fabricated through MOSIS using 2 μm double-metal CMOS technology. The RCAM chip was tested and its correct functionality has been fully verified.

A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses

An on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on a chip is described. The chip integrates 400 neurons and 40000 synapses with a 0.8- mu m double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Advanced architecture for a one-chip 16*16 digital switch

A one-chip 16*16 digital switch (SWEL) is presented which is designed for use in a wide variety of applications, ranging from digital mobile radio and satellite applications, to PCM switching systems (integrated services digital network). It provides a compact, low-power solution to perform in channel-controlled switching of 64-kb/s or 2-Mb/s channels. Both architecture and design issues are discussed in detail; a 1.2 mu m double metal CMOS technology was employed in the design. The multiplexed architecture allows for easy implementation of new application-specific requirements, making this circuit the cornerstone for new telecommunication switching products. >

A 10-b 40-MHz 0.8- mu m CMOS current-output D/A converter

A 10-b binary-weighted D/A digital-to-analog converter based on current division is presented. The effective resolution bandwidth is 5 MHz at a maximum clock frequency of 40 MHz. The circuit is integrated in a 0.8- mu m double-metal CMOS technology and the chip area is 0.4 mm/sup 2/. This particular converter was realized by constructing the bit currents through a careful combination of unit current sources and by limiting the driving voltage on the gates of the current switches.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

MOS implementation of winner-take-all network with application to content-addressable memory

Implementation of a winner-take-all (WTA) network suitable for implementing a nearest-match content-addressable memory (CAM) is presented. The resolution of the network in differentiating between words with large bit mismatches is presented. A measure of the time performance of the network is also given. A fully functional 16 word by 12 bit chip has been fabricated through MOSIS using 2 μm double-metal CMOS technology.

Capacitive-access CAM cell and its read/write circuit implementation

The implementation of a capacitive-access CAM cell along with its read/write circuitry are presented. Its advantages over a standard CAM cell are: feasibility of implementing multicell write operation, ready availability of masking of individual bits of a word for the write operation, and a higher order of cell data stability. A fully functional chip has been fabricated through MOSIS using 2 μm double-metal CMOS technology.

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses

A learning neural network LSI chip is described. The chip integrates 125 neuron units and 10K synapse units with the 1.0 mu m double-poly-Si, double-metal CMOS technology. Most of this integration has been realized by using a mixed design architecture of digital and analog circuits. The fully feedback connection network LSI can memorize at least 15 patterns with 50 mu s learning time for each pattern. Under the condition that each test vector keeps a Hamming distance of 6 from memorized pattern, a correct association rate of 98% is obtained. The relaxation time is 1 to 2 mu s. This chip consumes less than 7.5 W. >

Parameter variations in MOS CAM with a mutual inhibition network

A MOS implementation of mutual inhibition is combined with a standard content addressable memory (CAM) to produce a relaxative content addressable memory (RCAM) that automatically relaxes to the nearest match to an input. The operation of the RCAM is similar to the Hamming neural net. A simplified transistor model is employed to obtain a closed-form solution for the convergence time of the circuit, which can be used to design the circuit to meet specific performance goals. The model is used to find the settle time and the effects of parameter variation on the validity of the output. Chips were fabricated using 2- mu m double metal CMOS technology through MOSIS. >

A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation

A 64-kbyte snoopy cache memory was developed. The modified double word-line architecture with word-line buffers resulted in a large-size memory and a time-multiplex snoop operation by the pseudo-two-port method with a single-port cell. The flexible expandability was achieved by cascading multiple cache memories. The device was successfully implemented with 1.0- mu m double-polysilicon and double-metal CMOS technology. Low-power sense amplifiers and comparators limited power dissipation to 0.5 W at 40 MHz. >

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture

A self-learning neural network chip based on the branch-neuron-unit (BNU) architecture, which expands the scale of a neural network by interconnecting multiple chips without reducing performance, is described. The chip integrates 336 neurons and 28224 synapses with a 1.0- mu m double-poly-Si double-metal CMOS technology. The operation speed is higher than 1*10/sup 12/ connections per second per chip. It is estimated that the network scale can be expanded to several hundred chips. In the case of 200-chip interconnections, the network will consist of 3360 neurons and 5,644,800 synapses.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8- mu m double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit. >

A 30-MHz mixed analog/digital signal processor

A multiplying encoder architecture that is implemented in the design of a mixed analog and digital signal processor is presented. The processor is suitable for performing both high-speed A/D conversion and digital filtering in a single chip. The device can resolve the input with 8 b at 30 Msample/s and perform 28 multiply and 28 add operations per sample under typical conditions. The processor is designed for a 28-tap programmable FIR (finite impulse response) filter with analog input signal which can be used for waveform shaping of the modem to obtain the desired transmission performance for business satellite communication and mobile communication. The chip is fabricated in a 1- mu m double-polysilicon and double-metal CMOS technology. The chip size is 9.73*8.14 mm/sup 2/, and the chip operates with a single +5.0-V power supply. Typical power dissipation is 950 mW; 330 mW is dissipated in analog and 620 mW is in the digital block.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 15-ns 4-Mb CMOS SRAM

A 4-Mb SRAM with 15-ns access time and selectable (*4/*1) bit organization based on a 0.55- mu m triple-polysilicon double-metal CMOS technology is discussed. To achieve 15-ns access time, a sense amplifier with input-controlled PMOS loads (ICPLs), Y-controlled bit line loads, and transfer word driver are used. A built-in voltage regulator is provided to reduce the internal supply voltage to 4 V. Either *4 or *1 bit organization can be selected electrically, without pin connection changes. In the 0.55- mu m triple-polysilicon double-metal CMOS technology, the first polysilicon (polycide) is used for gate electrodes, the second (silicide) for the VSS lines of memory cells, and the third for resistive loads. The first metal is used for bit lines, and the second for the main word lines. The gate oxide thickness is 15 mm and the gate length is 0.55 mu m/0.65 mu m (NMOS/PMOS). The cell size is 3.4*5.6 mu m. The chip size is 7.7*18.6 mm. >

A 9-ns 1-Mbit CMOS SRAM

A 1-Mbit CMOS static RAM (SRAM) with a typical address access time of 9 ns has been developed. A high-speed sense amplifier circuit, consisting of a three-stage PMOS cross-coupled sense amplifier with a CMOS preamplifier, is the key to the fast access time. A parallel-word-access redundancy architecture, which causes no access time penalty, was also incorporated. A polysilicon PMOS load memory cell, which had a large on-current-to-off-current ratio, gave a much lower soft-error rate than a conventional high-resistance polysilicon load cell. The 1-Mbit SRAM, fabricated using a half-micrometer, triple-poly, and double-metal CMOS technology, operated at a single supply voltage of 5 V. An on-chip power supply converter was incorporated in the SRAM to supply a partial internal supply voltage of 4 V to the high-performance half-micrometer MOS transistors. >