Abstract
A 2D array implementation of image segmentation by a directed split and merge procedure is proposed. Parallelism is realized on two levels: one within the split and merge operations, where more than one merge (or split) may proceed concurrently, and the second between the split and merge operations, where several splits may be performed in parallel with merges. Both the split and merge operations are based on nearest neighbor communications between the processing elements (PEs), and facilitating low communication costs. The basic arithmetic operations required to perform split and merge are comparison and addition, allowing a simple structure of the PE as well as a hardwired control. A local of 512 bytes is sufficient to hold the interim data associated with each PE. A prototype PE has been constructed using 3 mu m double-metal CMOS technology. Scaling up to 0.8 mu m, it is possible to incorporate 32 PEs on a 5 cm/sup 2/ chip. With sufficiently large PE window sizes, image segmentation can be achieved in linear time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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