Double Dielectric Layer Research Articles

Electric field calculation and optimization for stress cone of DC cable joint based on the coaxial double-layer insulation model

This paper presents a DC electric field calculation and optimization algorithm for a coaxial double-layer insulation. The stress cone curve of a 320 kV DC cable joint was optimized utilizing the algorithm under different conditions. The obtained results show that the stress cone curve becomes steeper with an increase of the x-axis electric field. The curve also becomes steeper with a decrease of the temperature difference between the stress cone and the conductor screen. The interface charge density along the interface between the XLPE and SiR decreases continually with the reduction of the temperature difference. The thermo-electric coupling simulations were performed using finite element simulation software. The obtained results illustrate that the temperatures, electric fields and interface charge density of the stress cone obtained by the algorithm and the simulation are consistent. Moreover, the optimized stress cone curve achieves the intended x-axis electric field under the given temperature difference. It is appropriate to use the algorithm to optimize the electric field in the stress cone area due to the evident efficiency.

Interface resistivity and interfacial DC breakdown voltage of double-layer dielectrics

Double-layer dielectrics are widely used as insulation in electrical equipment, such as cable accessories. The interface between dielectrics is the weakest part of the insulation, which is critical to the overall insulation system. In this paper, the interface resistivity is studied as a parameter for evaluating the interface insulation performance. The interface resistivities of XLPE/SiR interfaces with different levels of roughness and pressures, as well as other interface types (XLPE/SiR, XLPE/EPDM, LDPE/SiR, LDPE/EPDM, HDPE/SiR, and HDPE/EPDM), were measured using an annular four-terminal electrode system. Moreover, interfacial ramped DC breakdown tests of XLPE/SiR interfaces with different levels of roughness and interface pressures were performed. As the roughness of the XLPE/SiR interface decreased, the interface resistivity increased from 5.10×1012 to 1.15×1013 Ω and the interfacial ramped DC breakdown voltage (U63.2%) increased from 20.48 to 36.80 kV. As the interface pressure of XLPE/SiR increased from 0.1 to 0.5 MPa, the interface resistivity increased from 9.72×1012 to 1.73×1013 Ω, and U63.2% increased from 26.49 to 53.61 kV. Interface resistivity is closely related to the contact morphology and surface resistivity, and an interface resistivity model is proposed to analyze the mechanism of the relationship between these factors. The interfacial ramped DC breakdown voltage has an obvious positive correlation with interface resistivity. Adopting interface resistivity as the characteristic parameter of interface insulation performance is beneficial for improving the reliability of interface insulation.

The strong continuous induction effect based on isotype heterojunction transistors with different polymer modifications

Abstract Organic thin film transistors (OTFTs) with a p-type pentacene/dioctylbenzothienobenzothiophene (C8BTBT) heterojunction have been fabricated. Insulating materials, including inorganic silicon oxide (SiO2), three polymers of Poly (4-vinylphenol) (PVP), Polystyrene (PS) and Polymethylmethacrylate (PMMA) were used as either dielectrics or modification layers. Our experiment shows that the morphology of C8BTBT films is highly relevant with the selection of the modification layer, which is due to the different physical/chemical properties of these polymers. The morphology difference of C8BTBT film then leads the pentacene film morphologies deposited upon C8BTBT to change again. Such fact clearly shows a to first-semiconductor to second-semiconductor continuous induction effect in our heterojunction OTFTs. Finally, it has been found the SiO2/PS double-layer insulator promotes the growth of the C8BTBT film and upper pentacene film. And a high mobility of 3.6 cm2/Vs for OTFTs with this dielectric and low cost copper (Cu) source/drain electrodes can be achieved.

Effect of traps-to-gate tunnel communication on C-V characteristics of MIS capacitors

The admittance measurements are commonly used for extraction of parameters of the traps located in the gate stack of the metal-insulator-semiconductor structures. The extraction procedures are based on models of the MIS structure, which are usually based on a modified Nicollian-Brews' equivalent circuit but do not comprise charge communication between the traps and the gate electrode. The model proposed in this work includes the traps-to gate tunnel communication and is used to discuss its impact on the capacitance-voltage characteristics of a MIS capacitor with a double-layer insulator gate stack.

Double layered dielectric elastomer by vapor encapsulation casting for highly deformable and strongly adhesive triboelectric materials

Triboelectric generators (TEG), based on contact electrification and electro-static induction, has received a significant attention because of their numerous applications. To improve the electrified surface charge density in TEG, increasing the surface area of dielectric materials or forming internal hollow structures are typically employed to increase capacitance. However, the fabrication processes of such structures are complex and time-consuming. Here, we provide a facile and cost-effective synthesis method for the porous PDMS based TEG via a novel vapor encapsulation casting (VEC). The double dielectric layer composed of the porous and dense PDMS layers are formed in-site through VEC. The thickness and the thickness ratio of the double dielectric layer can be precisely controlled by adjusting the uncured PDMS thickness and vapor penetration depth. The double dielectric layer TEG (DTEG) exhibits the improved harvesting performance because the porous dielectric layer increases the capacitance and compressibility, while the dense layer passivates the fully open pores which reduce the charging surface area as completely opening through the dielectric layer without contacting the bottom electrode. We obtain the maximum output voltage of 345 V and short circuit current of 3 μA/cm2 from DTEG having 0.95 porous thickness ratio, resulting 330% enhancement in the power output as compared to the dense PDMS based TEG. We further investigate the performance of DTEG under various operating conditions. We also demonstrate the operation of Bluetooth distance/temperature sensors using capacitors charged by DTEG.

An Amorphous Silicon Photo TFT with Si3N4/Al2O3 or HfO2 Double Layered Insulator for Digital Imaging Applications

This paper focuses on amorphous silicon photo thin-film transistors with double layered insulator using Si 3 N 4 /Al 2 O 3 or HfO 2 as candidates for the succession of Si 3 N 4 as a traditional insulator in the fabrication of hydrogenated amorphous silicon thin-film transistors. Whether for industry or for research, there is a need to investigate the use of thin gate insulators for these devices to overcome leakage current. Our investigations included direct and transfer characteristics in dark and under illumination, generated photocurrents, external quantum efficiency and responsivity. Performance is evaluated in terms of the dielectric thickness and nature. Improvements in the proposed structures regarding off-current, responsivity and quantum efficiency are achieved via these materials. Comparing with Si 3 N 4 /HfO 2 transistor, the Si 3 N 4 /Al 2 O 3 device shows the lowest off-current. The HfO 2 device presents the highest on-current when illuminated. The generated photocurrent is higher for Si 3 N 4 /HfO 2 transistor revealing a lower amount of trapped charge. Under illumination and for very thin thicknesses, both devices enhance the Si 3 N 4 device off-current and reach Si 3 N 4 single layer dielectric based phototransistor performance. external quantum efficiency and responsivity are higher in HfO 2 devices comparing with Al 2 O 3 devices. The results are promising and may support further investigations in order to develop high k gate insulators for MIS photo thin-film transistors.

The temperature effect to the compound electric field distribution of oil-paper insulation

This paper adopts a typical double-layer oil-paper insulation structure model, and obtains the mathematical expression of electric field distribution of oil-paper composite insulation. On the basis of the mathematical expression of the electric field distribution of oil-paper combination insulation, the numerical calculation results of the electric field distribution of oiled paper composite insulation are obtained. It is found that the temperature has little effect on the field strength distribution in transformer oil and paperboard under high AC content, and the temperature is low in low AC content. It has a great influence on the distribution of field strength in oil-paper insulation, especially the field strength in transformer oil.

A Study on TE Scattering by a Resistive Strip Grating Between a Double Dielectric Layer Using PMM

A Study on TE Scattering by a Resistive Strip Grating Between a Double Dielectric Layer Using PMM

Talking about the Application of High-tech Elements in the Innovative Design of Daily-use Ceramics

The relationship between technology and design is an eternal discussion as well as controversial topic. In the innovative design of daily-use ceramics, the advancement of technology has brought a lot of room for development in this field. This article will elaborate some effective combination of high-tech technology in daily-use ceramic design in the following four aspects: the combination of electronic technology and daily-use ceramics; the application of double-layer thermal insulation ceramics in the molding process; the analysis of the application of materials such as temperature-sensitive inks and the intervention of new healthy elements such as biochemical materials in the processing technology and surface treatment. Through these aspects to explore the current breakthrough in the design of daily-use ceramics.

The effect of electric conductivity on the structure of ceramic coatings prepared by cathode plasma electrolytic deposition

Abstract In the present study, Al2O3 (insulator), ZrO2 (ionic conductor) and (ZnO semiconductor) coatings were prepared by cathode plasma electrolytic deposition (CPED) method on stainless steel substrates. The surface morphologies and cross sections of the coatings were analyzed. The contributions to the electric current densities during the CPED process were studied. A double dielectric layers model was proposed to systematically study the effect of the electrical conductivities on the coating structures. The results showed that the coating structures and the electrical breakdown mechanism were closely related with the electrical conductivities of the coatings and the gas film. The different structures of the coatings can be attributed to the electric conductivity difference between the coatings and the gas film.

Conductivity and interface charge accumulation between XLPE and SIR for HVDC cable accessory

Interface charge accumulation between cross linked polyethylene (XLPE) and silicone rubber (SIR) is the key factor causing discharge failure for high voltage direct current (HVDC) cable accessory. However, the properties and mechanisms of interface charge behaviors in double-layer dielectric are not detailed. In the present work, dielectric performance and conductivity properties related to interface charge have been measured, and interface charge distributions between XLPE and SIR have been calculated based on Maxwell–Wagner polarization model. The experimental results indicate that charge conduction of SIR is larger than that of XLPE at room temperature, and the conductivity of SIR has a weak dependence on the temperature. By contrast, the conductivity of XLPE increases by three orders when the temperature increases from 25 °C to 90 °C, result in that the conductivity of XLPE exceed that of SIR at a certain temperature. The mismatch of conductivity properties for the two materials will cause charge accumulation at the interface. The interface charge density firstly decreases and then increases with the increasing temperature, and the polarity of charges are different for different temperature regions. Under 10 kV/mm, the transition temperature is about 40 °C. When the temperature exceeds the transition temperature, electric field in the two materials will reverse, and the polarity of interface charge will be changed accordingly.

Parylene-Based Double-Layer Gate Dielectrics for Organic Field-Effect Transistors.

We demonstrate high-performance and stable organic field-effect transistors (OFETs) using parylene-based double-layer gate dielectrics (DLGDs). DLGDs, consisting of parylene C as the upper layer and F as the lower layer, are designed to simultaneously provide good interface and bulk gate dielectric properties by exploiting the advantages of each gate dielectric. The structural effects of DLGDs are systematically investigated by evaluating the electrical characteristics and dielectric properties while varying the thickness ratio of each gate dielectric. The OFET with the optimized DLGD exhibits high performance and operational stability. This systematic approach will be useful for realizing practical electronic applications.

A charging method for electrets based on interfacial polarization

A charging method for electrets is proposed, based on interfacial polarization in double-layer media. It can achieve a high density and excellent stability of the charge storage as well as good uniformity of the surface potential distribution on electret materials. An equation for the charge accumulation at the interface of double-layer dielectrics is derived. FEP film electrets are successfully obtained by means of this charging method with an auxiliary PP-layer. The effect of the charging voltage on the storage performance shows that the surface potential of FEP films increases linearly with the charging voltage. This is in good agreement with the theoretical analysis. The effect of the charging temperature is ascribed to the change in conductivity of the two dielectrics, whereby the current density in particular across the PP layer increases with a rise in charging temperature. In addition, the charge is captured by deeper traps, while the deposition charge density increases.

Band structure of one-dimensional photonic crystal with graphene layers using the Fresnel coefficients method

In this paper, we have calculated the band structure of an instance of one-dimensional photonic crystal (1DPC) composed of double-layered dielectrics via the Fresnel coefficients method. Then, we supposed the addition of a thin layer of graphene to each dielectric layer and the given photonic crystal (PC) composed of dielectric–graphene composites. The effects of graphene layers on the PC band structure were evaluated. We found out that according to the effective medium theory unlike the TE polarization, the electric permittivity of the dielectric layers changed at TM polarization. As such, the band structure of PC for TM polarization changed, too. Moreover, instead of bandgap related to “zero averaged refractive index” an approximately omnidirectional bandgap appeared and a related bandgap to “[Formula: see text] = 0” disappeared. In addition, a new angular gap branch appeared at a new frequency at TM polarization in which the width of gap increased as the angle increased.

Band structure of one-dimensional doped photonic crystal with three level atoms using the Fresnel coefficients method

We consider a one-dimensional photonic crystal (1DPC) composed of double-layered dielectrics. Electric permittivity and magnetic permeability of this crystal depends on the incident electromagnetic wave frequency. We suppose that three level atoms have been added to the second layer of each dielectric and this photonic crystal (PC) has been doped. These atoms can be added to the layer with different rates. In this paper, we have calculated and compared the band structure of the mentioned PC considering the effect of added atoms to the second layer with different rates through the Fresnel coefficients method. We find out that according to the effective medium theory, the electric permittivity of the second layer changes. Also the band structure of PC for both TE and TM polarizations changes, too. The width of bandgaps related to “zero averaged refractive index” and “Bragg” increases. Moreover, new gap branches appear in new frequencies at both TE and TM polarizations. In specific state, two branches of “zero permittivity” gap appear in the PC band structure related to TM polarization. With increasing the amount of the filling rate of total volume with three level atoms, we observe a lot of changes in the PC band structure.

A Study on TM Scattering by a Conductive Strip Grating Between a Double Dielectric Layer

A Study on TM Scattering by a Conductive Strip Grating Between a Double Dielectric Layer

Ultrahigh energy density due to self-growing double dielectric layers at a titanium/sol–gel-derived amorphous aluminium oxide interface

Pursuing high-energy-density dielectric materials is desirable for the growing demands of energy storage for dielectric capacitors in modern electric power systems.

Photoelectric Memory Effect in Graphene Heterostructure Field-Effect Transistors Based on Dual Dielectrics

We report a photo and field (PF)-induced doping of a graphene-heterostructure field-effect transistor (graphene HFET) using a double-layered gate insulator consisting of narrow-bandgap insulator (NGI) and wide-bandgap insulator (WGI). The PF-induced doping in the graphene HFETs with variable NGIs (hafnium oxide, silicon nitride, and hexagonal boron nitride) are investigated, and consequently we reveal that this rewritable/erasable doping behavior is not limited to specific insulating materials, but unexceptionally accomplished when a step-like vertical band diagram, that is graphene/NGI/WGI, is fulfilled in the device. We clearly verify that this doping is originated from PF-induced charge transfer between graphene and defects at the NGI/WGI interface, and then the polarized charges at the NGI/WGI interface pretend to be “remote dopants”, shifting Dirac voltage of the device. The remote dopant is highly stable in the dark due to the presence of the adjacent insulators providing enormous energy barriers, b...

Efficient Threshold Voltage Adjustment Technique by Dielectric Capping Effect on MoS2 Field-Effect Transistor

In this letter, we demonstrate an efficient threshold voltage ( ${V}_{\mathrm{ th}})$ adjustment technique by depositing single or double dielectric layers on MoS2 field-effect transistors (FETs). We used Al2O3 and SiO2 as the capping layers on the MoS2 FET and observed different average ${V}_{\mathrm{ th}}$ shifts of −2.39 and +7.13 V, respectively. In order to further the controllability of the dielectric capping effect, the deposition of double dielectric layers, specifically Al2O3 on SiO2 and vice versa, was used for the first time. Consequently, the deposition of SiO2 on Al2O3 and Al2O3 on SiO2 shows an average ${V}_{\mathrm{ th}}$ shifts of +4.92 and +4.02 V, respectively. The defect charges in the dielectric layer can induce band bending in the MoS2 interface and adjust ${V}_{\mathrm{ th}}$ of the MoS2 FET. This result suggests a promising ${V}_{\mathrm{ th}}$ adjustment technique for transition-metal dichalcogenides-based FETs.

Dynamic characteristics analysis on interface polarization and depolarization of nonlinear double-layered dielectrics

The interface polarization model for double-layered nonlinear dielectrics is established based on nonlinear dielectrics with a+bE-type nonlinear conductivity (that is, the conductivity of dielectrics is a linear function of the electric field). The dynamic characteristics of the electric field, the interface charge, and the current during polarization and depolarization have been deduced analytically. The theoretical research results show that the electric, the interface charge, and the current have three kinds of models during the polarization: the exponential model, the hyperbolic tangent model, and the hyperbolic cotangent model. However, only the hyperbolic cotangent model occurs during the depolarization. The total current during polarization includes the DC steady state current and two absorption currents with different half-value period, and depolarization current contains two components with different half-value period. Because of the different polarities and values of two components, the depolarization current presents a variety of forms. Through theoretical derivation of the interface polarization of double-layered nonlinear dielectrics with a+bE-type nonlinear conductivity, the nonlinear interface polarization dynamic behavior is theoretically expounded and a foundation for future research into more complex nonlinear interface polarization is laid.