Double Gate Tunnel FET Research Articles

2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure

A continuous 2-D analytical drain current model of double-gate (DG) heterojunction tunnel field-effect transistors (HJTFETs) with a SiO2/HfO2 stacked gate-oxide structures has been presented in this paper. The surface potential model has been developed by considering the effect of accumulation/inversion charges and depletion region at source/channel and drain/channel junctions. The electric field-dependent band-to-band tunneling generation rate has been derived from the surface potential model. The tangent line approximation method has been used to calculate the drain current of DG HJTFETs. The developed model is valid for all regions (subthreshold to strong accumulation/inversion region) of operation. The model has been developed for Si/Ge hetero and Si homojunction-based tunnel field-effect transistor devices. The model is also applicable for other structures such as III–V materials-based InAs/GaSb DG HJTFET and silicon-on-insulator-based HJTFET. The analytical model results are validated by 2-D ATLAS simulation data.

Deep insight into linearity and NQS parameters of tunnel FET with emphasis on lateral straggle

Tunnel field-effect transistor (TFET) is considered to have superior device performance compared with DG-metal-oxide-semiconductor FET in terms of reduced off-state current and lower subthreshold swing. However, performance of a device solely depends on the accuracy in the fabrication process. This work presents a systematic methodology in small-signal-radio-frequency (RF) and linearity domain to analyse the effect of variation in lateral straggle caused by the variation tilt angle during ion implantation process. From previously published researches, it is intuitively established fact that the accurate evaluation of intrinsic components and estimation of linearity in short channel devices is crucial to access the range of application of the device. In this work, the authors have investigated the RF intrinsic parameter performances of a silicon double gate TFET having variation in lateral straggle from 1 to 5 nm. This study includes the analysis of non-quasi-static RF bias-dependent parameters such as intrinsic capacitances ( C gs , C gd ), gate-to-drain intrinsic resistance ( R gd ) and intrinsic time delay ( τ ). Similarly, the device linearity and reliability are investigated here in terms of higher-order transconductances ( g m2 and g m3 ), VIP 2 , VIP 3 , IMD 3 , IIP 3 and 1 dB compression point.

A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate–drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.

Analytical Modelling and Performance Analysis of Dielectric Pocket-Induced Double-Gate Tunnel Field-Effect Transistor

ABSTRACTIn this paper, a dielectric pocket-induced double-gate tunnel field-effect transistor is presented for improving the ON state current and suppressing the ambipolar conduction of the device. Introduction of dielectric pocket at the junction of both source and drain helps to tune the tunnelling barrier and subsequently controls the tunnelling current. A physics-based analytical model of surface potential and electric field is deduced by solving 2D Poisson's equation.Tunnelling current is then derived using Kane's model. The performance of this structure is then studied by varying the dielectric material of the pocket at source/drain junctions. Analytical results have been compared with the SILVACO ATLAS simulated results for verification of our model.

Compact Model for Double-Gate Tunnel FETs With Gate–Drain Underlap

A compact model for double-gate tunnel FETs (TFETs) with gate-drain underlap (DG u-TFET) is proposed which accounts for the alleviation of ambipolar current and Miller capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dg</sub> ) compared with double-gate tunnel FETs (DG TFET). The ON-state current degradation caused by the underlap is reproduced by extending the ideal DG TFET model with an effective resistance between the channel and the drain. Based on the device surface potential, the terminal charge model is developedwhich enables the possibility of circuit simulation and the terminal capacitance is further derived from the definition. This model captures the electrical characteristics of DG u-TFET explicitly and good agreement is achieved compared with TCAD simulation. After the model is implemented into HSPICE, an inverter is established and successfully simulated without convergence problem.

Advanced analytical modeling of double-gate Tunnel-FETs – A performance evaluation

The Tunnel-FET is one of the most promising devices to be the successor of the standard MOSFET due to its alternative current transport mechanism, which allows a smaller subthreshold slope than the physically limited 60 mV/dec of the MOSFET. Recently fabricated devices show smaller slopes already but mostly not over multiple decades of the current transfer characteristics. In this paper the performance limiting effects, occurring during the fabrication process of the device, such as doping profiles and midgap traps are analyzed by physics-based analytical models and their performance limiting abilities are determined. Additionally, performance enhancing possibilities, such as hetero-structures and ambipolarity improvements are introduced and discussed. An extensive double-gate n-Tunnel-FET model is presented, which meets the versatile device requirements and shows a good fit with TCAD simulations and measurement data.

Analytical modeling of asymmetric hetero-dielectric engineered dual-material DG-TFET

The present work aims to incorporate the benefits of asymmetric hetero-dielectric engineering into the already popular dual-material double-gate tunnel field-effect transistor. Here, Poisson's equation in 2D, incorporating appropriate boundary conditions, is solved to obtain the surface potential variation along the channel while considering Young's popular parabolic approximation technique. From the potential profile, the electric field is derived, and the drain current expression is then extracted analytically, integrating the band-to-band tunneling generation rate over the tunneling region using Kane's model. The dependence of surface potential, electric field, and tunneling current on the device parameters is analyzed by varying the biasing voltages, gate oxide thickness, body thickness, and gate metal work function, demonstrating agreement with TCAD simulation results. The performance of the device is compared with the earlier-reported structure of the dual-material gate hetero-dielectric TFET on the basis of channel potential, electric field, and drain current. The proposed device exhibits higher ON-state current, better ON---OFF current ratio, and suppressed short-channel effects. The results also demonstrate the superiority of the graded dielectric over the single-dielectric and hetero-dielectric double-gate TFET.

A temperature‐dependent surface potential‐based algorithm for extraction of threshold voltage in homojunction TFETs

AbstractIn this paper, we propose an algorithm to extract threshold voltage in homojunction tunnel field effect transistors (TFETs). Single gate TFET and double gate TFET are the geometries which are considered for verification of the method. Firstly, a generalized model of surface potential based on 2D Poisson equation for homojunction TFETs is developed. Secondly, the algorithm involves a number of geometrical operations on surface potential plots, which are performed computationally. From the plots of surface potential and the geometrical constructions, a parameter, range_point, is defined through mathematical formulations. The threshold voltage is determined by subjecting the range_point to a set of constraints which are found to be same for both the devices. The validity of the algorithm is confirmed by considering different parameters like drain voltage, gate oxide thickness, and temperature for both low‐k and high‐k gate dielectric materials in TFETs. The temperature variation is validated for a heterojunction TFET too using the same generalized model of surface potential.

Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis

In this paper, we investigate the impact of a drain-pocket (DP) adjacent to the drain region in Tunnel Field-Effect Transistors (TFETs) to effectively suppress the ambipolar current. Using calibrated two-dimensional device simulation, we examine the impact of DP in Double Gate TFET (DGTFET). We demonstrate the superiority of the DP technique over the existing techniques in controlling the ambipolar current. In particular, the addition of DP to a TFET is able to fully suppress the ambipolar current even when TFET is biased at high negative gate voltages and drain doping is kept as high as the source doping. Moreover, adding DP is complementary to the well-known technique of employ-ing source-pocket (SP) in a TFET since both need similar doping type and doping concentration.

Study of fully-depleted Ge double-gate n-type Tunneling Field-Effect Transistors for improvement in on-state current and sub-threshold swing

In this paper, a fully-depleted (FD) Ge double-gate (DG) n-type Tunneling Field-Effect Transistors (TFET) structure is studied in detail by two-dimensional numerical simulation. The simulation results indicated that the on-state current Ion and on-off ratio of the FD Ge DG-TFET increases about 1 order of magnitude comparing with the Conventional Ge DG-TFET, and Ion=3.95×10-5A/μm and the below 60mV/decade subthreshold swing S=26.4mV/decade are achieved with the length of gate LD=20nm, the workfuntion of metal gate Φm=0.2eV and the doping concentration of n+-type-channel ND=1×1018cm-3. Moreover, the impacts of Φm, ND and LD are investigated. The simulation results indicated that the off-state current Ioff includes the tunneling current at the middle of channel IB the gated-induced drain leakage (GIDL) current IGIDL. With optimized Φm and ND, Ioff is reduced about 2 orders of magnitude to 2.5×10-13A/μm with LD increasing from 40nm to 100nm, and on-off ratio is increased to 1.58×107.

An Accurate Drain Current Model of Monolayer Transition-Metal Dichalcogenide Tunnel FETs

A drain current model of 2-D monolayer (ML) transition-metal dichalcogenide (TMD) tunnel FETs (TFETs) is proposed. For better accuracy, the proposed model features the following two points: 1) the accurate lateral energy profiles considering the extension of the depletion width ( ${W}_{d}$ ) owing to the reduced dimensionality and 2) the spin- and valley-dependent complex band structure considering the spin-orbit coupling effect. The proposed model is validated by the tight-binding nonequilibrium green function simulation, in the case of ML MoS2 double-gate TFETs. By using the proposed model, the design guideline of ML TMD TFETs is presented.

Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure

The effect of ferro-electric (Fe) gate oxide on heterojunction and band-gap engineering based electro-statically doped source/drain (EDSD) double-gate Tunnel Field Effect Transistors (DG-TFETs), has been studied through 2-D TCAD device simulation. The combined effects of ferroelectric gate stack oxide and the hetero-junction, with low band gap material at source side and high band gap material in rest of the device helps to improve the performance of TFETs. The comparison of various low band gap source region materials shows that Hetrojunction Si-Ge EDSD Fe-DGTFET gives highest on-off current ratio of approx. 1013 and approximately 3mV/dec subthreshold swing. Further, comparison of different hetro-structures is done on the basis of analog characteristics and shows that Hetrojunction Si-Ge EDSD Fe-DGTFET gives lowest intrinsic delay of 1.576×10−11s, thus improving device speed. Moreover, some other analog parameters like gate to source capacitance, gate to drain capacitance, total capacitance, and transconductance and unity gain frequency are also studied to give an idea about improvement in device characteristics

Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field

In this work, the accuracy of a compact current–voltage (I–V) model for double-gate n-channel tunnel field-effect transistors (TFETs) is improve by considering outer and inner gate fringing field effects. The refined model is benchmarked against technology computer-aided design (TCAD) device simulations and compared against a previously published compact model. The normalized root-mean-square error for current in the linear region of operation (i.e., for 0.05 V drain voltage) is reduced from ∼593 to ∼5%.

Surface potential based modeling of charge, current, and capacitances in DGTFET including mobile channel charge and ambipolar behaviour

We present a surface potential based analytical model for double gate tunnel field effect transistor (DGTFET) for the current, terminal charges, and terminal capacitances. The model accounts for the effect of the mobile charge in the channel and captures the device physics in depletion as well as in the strong inversion regime. The narrowing of the tunnel barrier in the presence of mobile charges in the channel is incorporated via modeling of the inverse decay length, which is constant under channel depletion condition and bias dependent under inversion condition. To capture the ambipolar current behavior in the model, tunneling at the drain junction is also included. The proposed model is validated against TCAD simulation data and it shows close match with the simulation data.

Improved analytical model of surface potential with modified boundary conditions for double gate tunnel FETs

In this paper, an improved analytical model of the channel surface potential in the tunnel field effect transistors is established with modified boundary conditions considering the source and drain depletion widths, avoiding the deviation of the channel potential and the overestimate on the electric field. Based on the proposed surface potential model, the threshold voltage model is also developed with the transconductance change method. The influences of the channel and oxide structures on surface potential and threshold voltage are investigated. The good agreement is obtained by the comparison of the modeling results with the numerical simulation results, verifying the validation of the proposed model, and it also implied that this model will be helpful for the further investigation of TFETs.

Performance analysis of InAs- and GaSb-InAs-based independent gate tunnel field effect transistor RF mixers

This study compares the performance of radio frequency (RF) mixers employing independent-gate tunnel field-effect transistors (IG TFETs) based on homo (InAs) and heterojunctions (GaSb-InAs). A RF mixer circuit using double gate TFET of 20 nm is designed with the optimal biases on the two gates. IG TFETs used in the circuit simulation are developed with the help of a look-up table based Verilog-A code. The down conversion of RF mixers are operated at a frequency of 95 GHz. The figures-of-merit (FOM), conversion gain $$(G_{\mathrm {C}})$$ , noise figure (NF) and the average power consumption of the mixer circuits are studied along with the different device parameter variations, gate length $$(L_{\mathrm {g}})$$ , gate oxide thickness $$(T_{\mathrm {ox}})$$ and channel thickness $$(T_{\mathrm {ch}})$$ . Higher $$G_{\mathrm {C}}$$ and lower NF are achieved for heterojunction-based TFET mixers with respect to their parameter variations. An average power consumption of 168 and $$227.5\,{\upmu }\hbox {W}$$ is obtained for homo- and heterojunction-based TFET mixers, respectively.

Impact of device engineering on analog/RF performances of tunnel field effect transistors

The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (gm), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (FT), and maximum oscillation frequency (Fmax). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.

Two-dimensional analytical model for hetero-junction double-gate tunnel field-effect transistor with a stacked gate-oxide structure

A two-dimensional analytical model for hetero-junction double-gate tunnel FETs (DG TFETs) with a stacked gate-oxide structure is proposed in this paper. The effects of both the channel mobile charges and source/drain depletion regions on the channel potential profile are considered for the higher accuracy of the proposed model. Poisson’s equation is solved using the superposition principle and Fourier series solution to model the channel potential. The band-to-band tunneling generation rate is expressed as a function of the channel electric field derived from the channel potential and then integrated analytically to derive the drain current of the hetero-junction DG TFETs with a stacked gate-oxide structure using the shortest tunneling path. The effects of device parameters on the channel potential, drain current, and transconductance are investigated. Very good agreements are observed between the model calculations and the simulated results.

Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM

This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral spacing ( ${L}_ {\text {gap}})$ between the gates, and an underlap region ( ${L}_{\text {un}})$ between drain and back gate reduces state “0” degradation, which along with optimal biases, results in an improved Retention Time (RT) at 85 °C. The systematic design optimization increases RT from ~80 to ~300 ms with the use of ${L}_{\text {gap}}$ at 85 °C, which can be further improved to ~600 ms with the introduction of ${L}_{\text {un}}$ . The careful investigation shows the back gate scaled down to 25 nm with a front gate region of 100 nm, and operation even at elevated temperatures (125 °C). The insights into DG TFET DRAM operation in terms of individual as well as total lengths highlights the RT enhancement by a factor of 3 with constant total length (200 nm) and an improved scalability with total length scaled down to 160 nm. This paper provides new opportunities to realize TFET-based DRAM with improved RT, scalability, and high temperature operation.

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both ${I}$ – ${V}$ and ${G}$ – ${V}$ characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: ${g}_{m}/{I}_{\text {d}}$ , ${g}_{m}/{g}_{ds}$ , ${f}_{T}$ and ${f}_{T}/{I}_{d}{V}_{d}$ , and their temperature dependence from 25 °C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to $40~\text {V}^{-1}$ , for currents lower than 10 nA/ $\mu \text{m}$ ; and 3) higher unity gain frequency per unit power for currents below 10 nA/ $\mu \text{m}$ .