Double-gate Research Articles

Investigation into the effect of phenylalanine gating on anaerobic haem breakdown using the energy landscape approach.

We have recently demonstrated a novel anaerobic NADH-dependent haem breakdown reaction, which is carried out by a range of haemoproteins. The Yersinia enterocolitica protein, HemS, is the focus of further research presented in the current paper. Using conventional experimental methods, bioinformatics, and energy landscape theory (ELT), we provide new insight into the mechanism of the novel breakdown process. Of particular interest is the behavior of a double phenylalanine gate, which opens and closes according to the relative situations of haem and NADH within the protein pocket. This behavior suggests that the double phe-gate fulfills a regulatory role within the pocket, controlling the access of NADH to haem. Additionally, stopped-flow spectroscopy results provide kinetic comparisons between the wild-type and the selected mutants. We also present a fully resolved crystal structure for the F104AF199A HemS monomer, including its extensive loop, the first such structure to be completely resolved for HemS or any of its close homologues. The energy landscapes approach provided key information regarding the gating strategy employed by HemS, compensating for current limitations with conventional biophysical and molecular dynamics approaches. We propose that ELT become more widely used in the field, particularly in the investigation of the dynamics and interactions of weak-binding ligands, and for gating features, within protein cavities.

Impact of Interface Trap Charges on the Performance and Reliability of Heterojunction Hetero Dielectric Vertical Non-Uniform Channel Double Gate TFET

Impact of Interface Trap Charges on the Performance and Reliability of Heterojunction Hetero Dielectric Vertical Non-Uniform Channel Double Gate TFET

Modeling of β-Ga2O3 based double gate drain extended junction less FET and its parameter extraction methodology

Abstract A static current model of β—Gallium Oxide (β-Ga2O3) based double gate drain extended junction less field effect transistor (DG-DeJLFET) is proposed. The model consists of two voltage-controlled current sources connected in series. One of the current sources accounts for the operation of the junction less field effect transistor whereas, the other takes care of the drift region current. The model is formulated by considering the mobility degradation caused by moderately elevated electric fields. A parameter extraction methodology for this model is also proposed by considering the dominance of certain parameters in the specific regions of operation. In general, the parameter extraction technique is based on the variation in the device current behavior at moderate electric fields. The proposed parameter extraction methodology is validated by comparing the results with the data obtained from the TCAD simulation.

Ultrathin Rare-Earth Oxyhalides as High-κ van der Waals Layered Dielectrics.

Van der Waals (vdW) dielectrics are extensively employed to enhance the performance of 2D electronic devices. However, current vdW dielectric materials still encounter challenges such as low dielectric constant (κ) and difficulties in synthesizing high-quality single crystals. 2D rare-earth oxyhalides (REOXs) with exceptional electrical properties present an opportunity for the exploration of novel high-κ dielectrics. In this study, for the first time, the synthesis of a series of van der Waals layered gadolinium oxyhalides with thicknesses down to monolayer through a space-confined vdW epitaxy approach and demonstrating their application as a single-crystalline gate dielectric is reported. It exhibits a remarkable relative dielectric constant exceeding 17 and an impressive breakdown field strength of 13.5MVcm-1. The 2D transistors directly gated by the REOXs layer exhibit enhanced electron mobility and a low interface trap density. An ultrahigh on/off current ratio of 109 and a near-Boltzmann-limit subthreshold swing is achieved. The superior dielectric properties, combined with the universality and scalability of the production method (e.g., millimeter-scale films are achieved), demonstrate that 2D REOXs can serve as promising gate dielectrics for 2D electronics, thereby expanding the study of high-κ vdW materials and potentially providing new opportunities for the development of low-power electronic devices.

Multi-gate neuron-like transistors based on ensembles of aligned nanowires on flexible substrates

The intriguing way the receptors in biological skin encode the tactile data has inspired the development of electronic skins (e-skin) with brain-inspired or neuromorphic computing. Starting with local (near sensor) data processing, there is an inherent mechanism in play that helps to scale down the data. This is particularly attractive when one considers the huge data produced by large number of sensors expected in a large area e-skin such as the whole-body skin of a robot. This underlines the need for biological skin like processing in the e-skin. Herein, we present multi-gate field-effect transistors (v-FET) having capacitively coupled floating gate (FG) to mimic some of the neural functions. The v-FETs are obtained by deterministic assembly of ZnO nanowires on a flexible substrate using contactless dielectrophoresis method, followed metallization using conventional microfabrication steps. The spatial summation of two presynaptic inputs (applied at multiple control gates) of the transistor confirm their neuron-like response. The temporal summation (such as paired-pulse facilitation) by presented v-FETs further confirm their neuron-like mimicking with one presynaptic input. The temporal and spatial summation functions, demonstrated by the v-FET presented here, could open interesting new avenues for development of neuromorphic electronic skin (v-skin) with possibility of biological-skin like distributed computing.

Design and analysis of circular sheet junctionless double gate vertical nanotube (CSJL-DG-VNT) FET for DC/Analog/RF applications: device to circuit implementation

This paper investigates the influence of geometrical variations on the performance characteristics of a novel circular sheet junctionless double gate vertical nanotube (CSJL-DG-VNT) FET through 3D numerical simulations at sub-5nm technology node. Initially, the proposed device is compared with NWFET and NSFET, and shown favourable performance. The ION/IOFF current ratio is improved to 51.9% when gate length (Lg) is sweeping from 8 nm to 12 nm. The decrease in L g leads to enhanced analog/RF metrics such as gm, gm/Id, and fT. It was observed that opting for the shortest L g may be advantageous for certain parameters, albeit at the expense of others, depending on the specific application requirements. Further, while maintaining a constant L g , variations in the thickness tNT from 5 to 10 nm were carried out to evaluate the analog/RF performance for device optimization. It was observed that lower tNT (5 nm) values yielded improved IOFF current around ∼ 2 order and DIBL is 32.77% when compared with higher tNT (10 nm) due to ameliorated channel control from both inner and out gate of VNT. Subsequently, at an optimal L g and t NT the temperature (T) varied from 250 K to 450 K to analyze the device characteristics, indicating that a lower T should be favoured. Furthermore, the device is used for designing a common-source (CS) amplifier with tNT variations and noticed that at 5 nm of t NT outperforms highest gain (AV) ∼ 6.8 V/V when compared to 7 nm and 10 nm.

Capacitorless Dynamic Random Access Memory with 2D Transistors by One-Step Transfer of van der Waals Dielectrics and Electrodes.

Dynamic random access memory (DRAM) has been a cornerstone of modern computing, but it faces challenges as technology scales down, particularly due to the mismatch between reduced storage capacitance and increasing OFF current. The capacitorless 2T0C DRAM architecture is recognized for its potential to offer superior area efficiency and reduced refresh rate requirements by eliminating the traditional capacitor. The exploration of two-dimensional (2D) materials further enhances scaling possibilities, though the absence of dangling bonds complicates the deposition of high-quality dielectrics. Here, we present a hexagonal boron nitride (h-BN)-assisted process for one-step transfer of van der Waals dielectrics and electrodes in 2D transistors with clean interfaces. The transferred aluminum oxide (Al2O3), formed by oxidizing aluminum (Al), exhibits exceptional flatness and uniformity, preserving the intrinsic properties of the 2D semiconductors without introducing doping effects. The MoS2 transistor exhibits an extremely low interface trap density of about 3 × 1011 cm-2 eV-1 and a leakage current density down to 10-7 A cm-2, which enables effective charge storage at the gate stack. This method allows for the simultaneous fabrication of two damage-free MoS2 transistors to form a capacitorless 2T0C DRAM cell, enhancing compatibility with 2D materials. The ultralow leakage current optimizes data retention and power efficiency. The fabricated 2T0C DRAM exhibits a rapid write speed of 20 ns, long data retention exceeding 1,000 s, and low energy consumption of approximately 0.2 fJ per write operation. Additionally, it demonstrates 3-bit storage capability and exceptional stability across numerous write/erase cycles.

Negative capacitance source pocket double gate tunnel FET as a label-free dielectrically modulated biosensor

Abstract This article examines the potential use of Negative Capacitance Source Pocket Double Gate Tunnel Field Effect Transistor (NC-SP-DGTFET) as a biosensor capable of detecting the biomolecules present in the nanocavity. The proposed biosensor incorporated a gate dielectric engineering along with the channel engineering method and asymmetrical doping at source and drain regions. In addition, a nanocavity is formed by selectively removing a section of the gate dielectric at the source and drain ends to accompany the biomolecules in the device. The biosensing performance measures Threshold Voltage Sensitivity (S_(V_th )), ION/IOFF Current Ratio Sensitivity (S_(I_oN/I_OFF )), and Drain Current Sensitivity (S_(I_DS )), with 60.3, 372.3, and 395.4 respectively are observed with neutral charge of biomolecules. The investigation involves biomolecules with positive and negative charges, which are tested under different dielectric constants in the nanocavity. In addition, an extensive investigation of a partially filled nanocavity caused by steric hindrance has been presented to capture the current situation. The study examined several scenarios with partially filled nanocavities to analyze the sensitivity characteristics, including convex, concave, increasing, and decreasing step profiles, as well as the positioning of the probe in an asymmetric manner. The study compares several sensitivity characteristics of the NC-SP-DGTFET with existing biosensors to determine the effectiveness of the proposed biosensor. The NC-SP-DGTFET biosensor outperforms traditional TFET-based biosensors by using a ferroelectric material as the oxide material. This choice of material enhances the subthreshold slope, increases gate control over the channel, and demonstrates its suitability for low-power biosensor design.

Impact of Interface Traps on Reliability in Negative Capacitance Source Pocket Double Gate TFET

Impact of Interface Traps on Reliability in Negative Capacitance Source Pocket Double Gate TFET

Investigation of Single Event Transient Effect in Double-Gate InP-Based HEMT

An investigation of single event transient (SET) effect in double-gate InP-based HEMT (DG-HEMT) was conducted by simulations. The effects of different drain voltages (V DS), ion incident positions and angles, linear energy transfer (LET) on SET effect in DG-HEMT were comprehensively analyzed. The simulation results showed that the incident position in gate for DG-HEMT is the most sensitive to SET effect. A higher transient peak drain current (I peak) induced by SET effect was obtained with the higher LET and V DS. At the larger LET and V DS, more electrons were produced by the larger impact ionization rate, leading to the higher I peak. As the incident angle reduces, the track length of incident ions become longer, that is, the sensitive area becomes larger, resulting in the higher I peak. Compared with the single gate InP-based HEMT, the irradiation resistance of device with double gate is improved significantly.

Heterogeneous monolithic complementary thin-film transistor with n-channel polycrystalline-silicon and upper p-channel double-gate polycrystalline-germanium thin-film transistors on a glass substrate

Abstract In this study, we developed a heterogeneous and monolithic complementary thin-film transistor (CTFT) on a glass substrate. The design integrates an n-channel (n-ch) top gate (TG) polycrystalline-silicon (poly-Si) thin-film transistor (TFT) on the bottom layer with a p-channel (p-ch) double-gate (DG) polycrystalline-germanium (poly-Ge) TFT on the upper layer. The poly-Si layer was crystallized through continuous-wave laser lateral crystallization, whereas the DG poly-Ge TFT on the upper layer was fabricated using metal-induced crystallization at 500 °C, employing copper as a catalyst. The inverter operation exhibited a transition voltage of 0.9 V at VDD = 4.0 V, aligning with theoretical predictions. During the dynamic operation of the CMOS inverter, the pull-up delay time was longer than the pull-down delay. This delay disparity is attributed to the lower on-current of the p-ch poly-Ge TFT. Potential enhancements include employing a multilayered p-ch poly-Ge TFT or incorporating germanium-tin (Ge1−x Sn x ) as the channel material.

An Analytical Subthreshold I–V Model of SiC Double Gate JFETs

ABSTRACTSiC double gate (DG) junction field effect transistor (JFET) is promising for low‐noise and high‐temperature electronics. Existing studies indicate that JFETs can be considered a special case of MOSFETs when the oxide layer thickness approaches zero. In this article, we exploited the structural similarity between the DG JFETs and the DG MOSFETs. By obtaining the 2D Poisson's equation for the DG MOSFETs and deriving the limits, we developed a model for calculating the channel current of SiC DG JFETs in the subthreshold region. The model is derived from device physics, requiring no fitting parameters and offering relatively low computational complexity. The results indicate that, whether for enhancement mode or depletion mode JFETs, the calculated values of this model are in good agreement with the 2D numerical analysis results obtained from Silvaco Atlas. Moreover, for enhancement mode JFETs, even when significant short‐channel effects occur, the subthreshold current can still be well predicted. In addition, the model displays predictive capability for the depletion‐mode JFETs.

Influence of Varying Recessed Gate Height on Analog/RF Performances of a Novel Normally-Off Underlapped Double Gate AlGaN/GaN-based MOS-HEMT

Current transistor technology has issues with off-state current which reduces power efficiency. The paper presents a novel Normally-off Underlapped Dual Gate (U-DG) AlGaN/GaN MOS-HEMT device to tackle these issues. A novel dual recessed gate technology is implemented in the device which deepens the depletion region, creating a strong barrier that prevents current flow at negative gate voltage. The study investigates various recessed gate heights’ impact on analog and RF performance. Key parameters like drain and gate Currents, transconductance, and transconductance generation factor were analyzed, alongside intrinsic capacitance, gate capacitance, intrinsic resistance and maximum oscillation frequency. Results indicate that a 19 nm recessed gate height offers optimal performance. It is the only one to achieve a normally off state and a substantial 45% increase in transconductance compared to other heights. This research provides crucial insights into designing efficient Normally-off U-DG AlGaN/GaN MOS-HEMT devices, particularly relevant for low-power applications.

Monolithic β-Ga2O3 bidirectional dual-gate MOSFET

We report a monolithic bidirectional dual-gate metal–oxide–semiconductor field-effect transistor fabricated on epitaxially grown β-Ga2O3, demonstrating efficient two-way conduction and blocking. It features two independently controlled gates and operates in four distinct modes, offering flexibility in managing current and voltage in the first and third quadrants. This versatility makes it ideal for various power conversion system applications. The device operates at a low negative threshold voltage (∼−2.4 V for both gates), with a zero turn-on drain voltage and an on-resistance of approximately 500 Ω· mm. It exhibits a high on/off current ratio of 107 in all three conducting modes. In the blocking mode, the device breakdown was measured to be higher than ± 400 V. The estimated breakdown field and power figure of merit for the device are 0.4 MV/cm and 2.1 MW/cm2, respectively.

Tailoring the performance of the multidimensional electrostatically formed nanowire gas sensor

Abstract Multi-gate field effect transistors (FETs) based on silicon-on-insulator (SOI) have been popular for several decades due to their improved electrostatic control of the channel current between the source and the drain. Chemical sensors based on such multi-gate FET platform can leverage this improved electrostatic control to detect gases at very low concentration with ultrahigh sensitivity. Electrostatically formed nanowire (EFN) is a multiple-gate FET device which has proven to be an excellent platform for detecting volatile organic compounds and gases. In case of such multi-gate FET sensors, it is imperative to rigorously understand the influence of each gate in controlling the sensing performances. Using palladium nanoparticles decorated EFN (Pd-EFN) as an example, the current work presents a detailed methodology for determining the operating parameters for maximal sensing performances of the Pd-EFN sensor towards hydrogen sensing. We observed that a single operating point does not yield best results with regard to sensor response, dynamic range, and power efficiency. By optimising the operating points (by varying the different gate biases), a sensor response of 107 % was reached even at low concentrations of hydrogen (500 ppm) which is significantly lower than the lower explosive limit of 4% and a tunable dynamic range over three decades (4-8000 ppm) was obtained. Also, the sensor response was not compromised at low driving voltages (100 mV) thus contributing to low power consumption of the sensor. Such a correlation between the working point of the transistor and the various sensor performance metrics (maximum sensor response, dynamic range etc ) has not been studied before to the best of our knowledge and this study can be extended to EFN for other gases and any other multi-gate FET sensors (not limited to Si based sensors).This study can pave the way for effective design of future multi-gate transistors for gas sensing.

A printed gallium oxide dielectric for 2D transistors

A printed gallium oxide dielectric for 2D transistors

Impact of deep and tail trap states on the electrical performance of double-gate ZnO thin film transistors

Abstract Traps in ZnO thin film transistors (TFTs) affect the electrical characteristics of the device. Traps originate primarily due to the disordered nature of the deposited semiconductor channel or are present at the ZnO and gate-dielectric interface. This work studies the effect of traps in double-gate ZnO TFTs using technology computer-aided design. The grain boundary and interface traps are assumed to be localized at the ZnO/SiO2 interface and are defined within the energy bandgap of ZnO using a double-exponential function. The traps are assumed to be of the acceptor type. The concentration of tail states is assumed to be 103 times more than in the deep state, while the characteristic temperature of deep state traps is assumed to be higher than the tail states. In common mode operation (i.e. both top and bottom gates are shorted), the tail states dominate the device characteristic compared with the deep state, while in independent mode (i.e. both gates are biased independently) the deep state traps affect the device characteristics more than the tail states.

Built-in Bernal gap in large-angle-twisted monolayer-bilayer graphene

AbstractAtomically thin materials offer multiple opportunities for layer-by-layer control of their electronic properties. While monolayer graphene (MLG) is a zero-gap system, Bernal-stacked bilayer graphene (BLG) acquires a finite band gap when the symmetry between the layers’ potential energy is broken, usually, via a displacement electric field applied in double-gate devices. Here, we introduce a twistronic stack comprising both MLG and BLG, synthesized via chemical vapor deposition, showing a Bernal gap in the absence of external fields. Although a large (~30°) twist angle decouples the MLG and BLG electronic bands near Fermi level, proximity-induced energy shifts in the outermost layers result in a built-in asymmetry, which requires a displacement field of 0.14 V/nm to be compensated. The latter corresponds to a ~10 meV intrinsic BLG gap, a value confirmed by our thermal-activation measurements. The present results highlight the role of structural asymmetry and encapsulating environment, expanding the engineering toolbox for monolithically-grown graphene multilayers.

Impacts of Cavity Thickness and Insulating Material on Dielectric Modulated Trench Junction-less Double Gate Field Effect Transistor for Biosensing Applications

Introduction: This work represents the influence of gate dielectric, and the nano-cavity gap of a dielectric modulated trench gate Junction-less Double Gate Field Effect Transistor (JL-DGFET) on the different performance indicators is investigated considering the Low-Frequency Noise. Methods: It is noted that the gate dielectric and the nanogap, both parameters, have a substantial influence on the sensing capacity and performance of noise of the device. Results: A double gate suitable dielectric material and cavity thickness can effectively improve the biosensor’s sensitivity with a minimum amount of noise. Conclusion: The sensitivity is found to increase up to 9.5 for dielectric constant, k = 3.57 and 6.5 for dielectric constant, k = 2.1.

Impact of high-k insulators on electrical properties of junctionless double gate strained transistor

High-k dielectric insulators are required to reduce leakage and increase transistor performance. They are able to impact the mobility of carriers in transistors positively, leading to better device performance in advanced transistor architecture. Nevertheless, an in-depth analysis of how high-k dielectric insulators influence transistor characteristics must be carried out to determine their suitability. The objective of this study is to investigate the impact of high-k insulators towards electrical properties of junctionless double gate strained transistor. The simulation works is done using process/device simulator Silvaco Athena/Atlas. Based on the retrieved results, the magnitude of I<sub>ON</sub>, on-off ratio, g<sub>m</sub>, and C<sub>int</sub> for TiO<sub>2</sub>-based device are approximately 63%, 99%, 62%, and 89% respectively higher than the lowest permittivity material-based device. The TiO<sub>2</sub>-based device also exhibits the lowest magnitude in I<sub>OFF</sub> and SS compared to others. However, a significant degradation in f<sub>T</sub> magnitude have been observed for TiO<sub>2</sub>-based device significantly due to its large capacitances