Double-gate Silicon-on-insulator Research Articles

Analysis of Lanthanum Oxide Based Double-Gate SOI MOSFET using Monte-Carlo Process.

This work proposes a Double-Gate (DG) MOSFET with a Single Material made of Silicon On-Insulator (SOI). The Lanthanum Oxide material with a high k-dielectric constant has been used as an interface between two gates and the channel. The Monte Carlo analysis has been used to determine the Conduction Band Energy (Ec) profiles and electron sheet carrier densities (ns) for a Silicon channel thickness (tsi) of 10 nm at 0.5 V gate drain-source voltages. The transverse electric fields are weak at the midchannel of DG SOI MOSFETs, where quantum effects are encountered. The Monte Carlo simulation has been confirmed to be effective for high-energy transport. A particle description reproduces the granularity property of the transport for nanoscale modeling. This work utilizes a Monte Carlo (MC) Simulation for the proposed Double Gate Single Material Silicon On Insulator MOSFET with (La2O3=2 nm) as dielectric oxide on upper and lower gate material. The electrical properties of the DG SOI MOSFETs with Lanthanum Oxide were analyzed using Monte Carlo simulation, including the conduction band energy, electric field, potential distribution, particle movement, and average velocity. The peak electric field (E) simulation results and an average drift velocity (υavg) of 6Í105 V/cm and 1.6Í107 cm/s were obtained, respectively. The conduction band energy for the operating region of the source has been observed to be 4 % to the drain side, which obtained a value of -0.04 eV at the terminal end. This proposed patent design, such as double-gate SOI-based devices, is the best suggestion for significant scalability challenges. Emerging technologies reach the typical DG SOI MOSFET's threshold performance when their geometrical dimensions are in the nanometer region. This device based on nanomaterial compounds has been more submissive than conventional devices. The nanomaterials usage in the design is more suitable for downscaling and reducing packaging density.

Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog performance

Negative Capacitance Field Effect Transistors (NCFETs) offer the possibility of enhancing channel length scalability, with a key challenge being to ensure hysteresis and Negative Differential Resistance (NDR) free behavior. In this context, through TCAD-based simulations, for a symmetric Double-gate Silicon-on-Insulator (DG-SOI) baseline architecture with a Metal–Ferroelectric–Insulator–Semiconductor (MFIS) configuration, we first examine the root cause of NDR as being the FE layer with a small number of strongly coupled domains, which allows the drain to lower the surface potential (ΨSs) and internal gate voltage (Vint) on the source side. With this understanding of NDR, the inclusion of a paraelectric (PE) layer on the drain side of the gate stack, by splitting the stack into two halves laterally, while keeping the thickness of the stack unchanged, minimizes the drain’s influence on the source-sided electrostatics. This results in the mitigation of NDR effects along with superior analog performance parameters, thus making these FE–PE gate stack-based NCFET devices suitable for analog circuit applications.

Quantum Enhancement of a S/D Tunneling Model in a 2D MS-EMC Nanodevice Simulator: NEGF Comparison and Impact of Effective Mass Variation.

As complementary metal-oxide-semiconductor (CMOS) transistors approach the nanometer scale, it has become mandatory to incorporate suitable quantum formalism into electron transport simulators. In this work, we present the quantum enhancement of a 2D Multi-Subband Ensemble Monte Carlo (MS-EMC) simulator, which includes a novel module for the direct Source-to-Drain tunneling (S/D tunneling), and its verification in the simulation of Double-Gate Silicon-On-Insulator (DGSOI) transistors and FinFETs. Compared to ballistic Non-Equilibrium Green’s Function (NEGF) simulations, our results show accurate I vs. V and subthreshold characteristics for both devices. Besides, we investigate the impact of the effective masses extracted Density Functional Theory (DFT) simulations, showing that they are the key of not only the general thermionic emission behavior of simulated devices, but also the electron probability of experiencing tunneling phenomena.

Impact of carrier quantum confinement on the short channel effects of double-gate silicon-on-insulator FINFETs

In this work, we use a center potential based approach to determine the electrostatics viz. threshold voltage (Vth), Sub-Threshold Slope and Drain Induced Barrier Lowering (DIBL) for Fully Depleted (FD) Undoped Symmetric Double-Gate (DG) Silicon-on-Insulator (SOI) FINFETs over a wide range of Channel Lengths (Lg) and drain voltages (Vd). Based on this approach, a comparison of the electrostatics of Undoped Symmetric Double-Gate (DG) Silicon-on-Insulator (SOI) FINFETs is presented between the semi-classical and quantum confinement cases for two different SOI fin thicknesses of Tfin=2nm and Tfin=7nm, respectively. For both cases, it is observed that the threshold voltage roll-off and DIBL is greater in the quantum confinement case than in the semi-classical case. This seemingly counter-intuitive trend also implies that the channel length corresponding to the transition from long channel to short channel behavior (Lmin) is also lower in the semi-classical case compared to the quantum confinement case. This behavior is explained by comparing the Lateral Electric field (along the channel length) with the Electric Field along the thickness of the SOI fin for Tfin=2nm and Tfin=7nm over a wide range of gate and drain voltages. This analysis suggests that quantum confinement adversely affects the short channel effects and leads to an increase in the Lmin compared to the semi-classical case. These results for Lmin clearly illustrate the importance of the need to include the quantum confinement effects while evaluating the electrostatics performance and scalability of symmetric DG SOI FINFETs.

Full quantum simulation study of a nano tri-material double gate silicon-on-insulator MOSFET

We present 2D full quantum simulation based on the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green’s function formalism, for a novel multiple region silicon-on-insulator (SOI) MOSFET device architecture – tri-material double gate (TMDG) SOI MOSFET. This new structure has three materials with different work functions in the front gate, which show reduced short-channel effects such as the drain-induced barrier lowering and subthreshold swing, because of a step function of the potential in the channel region that ensures the screening of the drain potential variation by the gate near the drain. Also, the quantum simulations show the new structure significantly decreases leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional and dual material DG SOI MOSFET.

Nonequilibrium Green's function treatment of a new nanoscale dual-material double-gate MOSFET

In this paper the electrical characteristics of a novel nanoscale double-gate (DG) silicon-on-insulator(SOI) MOSFET, in which the front gate consists of two materials with different work functions, have been investigated by a full quantum-mechanical simulation. The simulations have been done by the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The quantum simulation results show that the new structure decreases significantly the leakage current and drain conductance and increases the on–off current ratio and voltage gain as compared to the conventional DG SOI MOSFET. In this new structure, the potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain, resulting in suppressed short-channel effects like the drain-induced barrier lowering (DIBL) and hot-carrier effect.

Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS. From the study, we conclude that alternative devices like double-gate silicon-on-insulator (DGSOI) are better candidates in terms of performance, robustness and PVT insensitivity as compared to bulk circuits for both static CMOS and pseudo NMOS logic families. We also study the performance and robustness comparisons of bulk CMOS and DGSOI subthreshold basic logic gates with and without parameter variations and we observe 60-70% improvement in power delay product and roughly 50% better tolerance to PVT variations of DGSOI subthreshold logic circuits compared to bulk CMOS subthreshold circuits at the 32 nm node.

Hole Mobility in Ultrathin Double-Gate SOI Devices: The Effect of Acoustic Phonon Confinement

We show that the effect of phonon confinement in ultrathin double-gate silicon-on-insulator (DGSOI) transistors on hole mobility is weaker than that predicted for electron mobility. To do so, confined phonon modes in SOI devices are computed, employing an elastic continuum model of acoustic phonons in a three-layer structure. A self-consistent k middot p-Poisson solver has been developed for the valence-band structure calculation, and Kubo-Greenwood formalism is used to compute the hole mobility in ultrathin DGSOI transistors under the combined effect of confined phonon and surface-roughness scattering.

Phonon-Limited Electron Mobility Behavior and Inherent Mobility Reduction Mechanism of Ultrathin Silicon-on-Insulator Layer with (111) Surface and Ultrathin Germanium-on-Insulator Layer with (001) Surface

One-dimensional self-consistent calculations and relaxation time approximations are used to study the phonon-limited electron mobility behavior of the inversion layer at room temperature for ultrathin body Si(111) and Ge(001) layers in single-gate (SG) and double-gate (DG) silicon-on-insulator (SOI) and germanium-on-insulator (GOI) metal–oxide–semiconductor (MOS) field-effect transistors (FETs). Assuming a 5-nm-thick SOI layer, it is shown that intravalley phonon scattering (acoustic-phonon scattering) in the DG SOI MOSFET inversion layer is strongly suppressed within a range of medium and high effective field (Eeff) values; DG SOI MOSFETs have higher phonon-limited electron mobility than SG SOI MOSFETs. Many simulations strongly indicate that, for medium Eeff values, the suppression of acoustic-phonon scattering in a 5-nm-thick DG SOI MOSFET primarily stems from the reduction of the form factor (F00) value. Although similar phenomena are observed in approximately 7-nm-thick GOI layers with a Ge(001) surface, it is shown that there is little merit in using the Ge(001) surface for DG GOI MOSFETs.

Empirical Models of Phonon-Limited Electron Mobility for Ultrathin-Body Single-Gate and Double-Gate Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors with (001) or (111) Si Surface Channel

We propose empirical models of the phonon-limited electron mobility of single-gate (SG) and double-gate (DG) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) with (001) or (111) Si surface channels. Electron mobility models are functions of the SOI layer thickness and the effective electric field. The proposed phonon-limited electron mobility models accurately reproduce self-consistent simulation results. The purpose of the study is to produce reliable mobility models that can be applied to commercial device simulators. Using the electron density derived from quantum simulations and the proposed empirical electron mobility models, drain current vs gate voltage (Id–Vg) and transconductance vs gate voltage (gm–Vg) characteristics of SG and DG SOI MOSFETs with 10- and 3-nm-thick SOI layers, (001) or (111) surfaces, are calculated to examine the potential of the proposed mobility models. The results are compared with commercial two-dimensional (2-D) device simulation results (DEESIS simulator). It has been shown that the DESSIS results are not reliable when the device has a sub-10-nm-thick SOI layer. The proposed model, on the other hand, clearly reproduces the effects of Si surface orientation and device structure. The proposed models are useful for a simple estimation of the drive current of various SOI MOSFETs and for reducing the computation time in device simulations and circuit simulations.

Features of phonon-limited electron mobility behavior of double-gate field-effect transistor with (111) Si surface channel

One-dimensional self-consistent calculations and relaxation time approximations are used to study the phonon-limited electron mobility of the inversion layer at room temperature for ultrathin body Si (111) layers in single-gate (SG) and double-gate (DG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFET’s). Assuming a 5-nm-thick SOI layer, it is shown that intravalley phonon scattering (acoustic-phonon scattering) in the DG SOI MOSFET inversion layer is strongly suppressed within a range of medium effective field (Eeff) values; DG SOI MOSFETs have higher phonon-limited electron mobility than SG SOI MOSFET’s. Many simulations strongly suggest that the suppression of acoustic-phonon scattering in a 5nm TSOI DG SOI MOSFET primarily stems from the reduction of the form factor (F00) value within medium Eeff values.

A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs

In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed

Analysis of Static and Dynamic Performance of Short-Channel Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors for Improved Cutoff Frequency

A comprehensive analysis of the static and dynamic characteristics of deep submicron double-gate (DG) and single-gate (SG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented, based on two-dimensional (2D) numerical simulations for high-frequency analog applications. Results from the static analysis show that a DG MOSFET offers excellent performance with respect to short-channel immunity, drain current enhancement and improvement in transconductance, Early voltage and voltage gain. We also analyze the impact of volume inversion (VI) on the performance of DG devices under saturation conditions, and investigate, in detail, the level of current enhancement and the bias conditions under which it can be achieved. Results show that a current as high as 15 times that of single-gate (SG) MOSFETs can be achieved in DG devices at a transconductance-to-current ratio of 25 V-1. Analysis of the dynamic part shows that due to the dual-gate structure, DG devices offer nearly twice the gate-source capacitance as compared to SG devices, thus limiting the cutoff frequency at higher gate voltages and longer channel lengths. At shorter channel lengths (L≤50 nm) and low gate overdrive voltages (<400 mV), DG devices show a significant improvement in cutoff frequency compared to SG devices, thus making double-gate SOI MOSFETs potential candidates for high-frequency analog applications.

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET—Two-Dimensional Analytical Modeling and Simulation

In this paper, we present the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, i.e., a dual-material double-gate (DMDG) SOI MOSFET, exhibits significantly reduced short-channel effects (SCEs) when compared with the DG SOI MOSFET. SCEs in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage, and drain-induced barrier lowering. A model for the drain current, transconductance, drain conductance, and voltage gain is also discussed. It is seen that SCEs in this structure are suppressed because of the perceivable step in the surface-potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

An improved semi-classical Monte-Carlo approach for nano-scale MOSFET simulation

A conventional Monte-Carlo simulator has been extended to include electrostatic and transport effects that are most relevant for the analysis of nano-scale MOSFETs with either bulk or single and double gate silicon-on-insulator (SOI) architectures and silicon film thickness down to approximately 10 nm. Corrections to the self-consistent electrostatic potential and a new model for the surface roughness scattering have been included. The effectiveness of the approach has been tested simulating carrier transport in a 25 nm double gate SOI MOSFET. The simulation results point out the strong influence of the scattering on the ON current even in these ultra-scaled devices.

Gate bias symmetry dependency of electron mobility and prospect of velocity modulation in double-gate silicon-on-insulator transistors

We report on detailed room-temperature transport properties of a 17nm thick double-gate silicon-on-insulator (DGSOI) transistor. We find that when the electron gas is transferred between the top and the bottom of the silicon-on-insulator (SOI) layer by changing the gate bias symmetry (i.e., applying the gate biases in a push–pull fashion), while keeping the carrier density constant the maximum mobility occurs when the electron gas symmetrically occupies the whole SOI slab. The observed mobility behavior is the fingerprint of volume inversion∕accumulation. This gate bias symmetry dependency of the mobility suggests that DGSOI devices intrinsically can be operated in a velocity modulation transistor (VMT) mode. In the experimental gate bias window, the maximum velocity∕mobility modulation is ∼40%. The VMT transconductance exceeds conventional single-gate transconductance when electron density is above ∼5.3×1016m−2. Improvements of the observed VMT operation in thin DGSOI devices are discussed.

Double gate silicon on insulator transistors. A Monte Carlo study

Electron transport properties in double-gate-silicon-on-insulator (DGSOI) transistors are comprehensively studied. Quantum effects are analyzed by self-consistently solving the 1 D Poisson and Schroedinger equations. Once the electron distribution is known, the Bolztmann transport equation is solved by the Monte Carlo method, and the role of volume inversion is analyzed both at room and at lower temperatures. A comparison between symmetrical-gate and asymmetrical-gate configurations is also provided, showing the superior performance of symmetric devices. Finally, velocity overshoot is also studied. Monte Carlo simulations were performed to clarify the dependence of velocity overshoot effects on the low-field mobility, channel inversion charge and silicon layer thickness. We show that electron mobility is mainly determined by the increase in the phonon scattering rate as the silicon thickness is reduced, i.e., the lower the silicon thickness the lower the electron mobility, while velocity overshoot effects for ultrathin DGSOI inversion layers are dominated by the reduction of the average conduction effective mass, i.e., the lower the silicon thickness the higher the velocity overshoot peak.

Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications

An analytical model is developed for laterally asymmetric channel (graded channel (GC)) design in double gate (DG) silicon-on-insulator (SOI) MOSFETs. Based on modeling, 2D simulation and experimental results, we show DG MOSFETs with laterally asymmetric channel engineering can achieve high values of saturation drain current, exceptionally high values of Early voltage (>1600 V) and intrinsic DC gain of 70–80 dB for L eff=1.64 μm, well in excess of those reported so far. Results of GC DG MOSFETs have also been compared with experimental and simulated data of uniformly doped double and single gate (SG) SOI MOSFETs. The analysis takes into account the effect of length and doping of the high and low doped regions to develop a compact model suitable for device design. The results of analytical model agree well with experimental and simulation data. We propose design guidelines for overall optimum performance of GC DG MOSFETs for realizing future high performance analog circuits.

Image and exchange-correlation effects in double gate silicon-on-insulator transistors

We have studied the influence of the image and exchange-correlation effects in double-gate silicon on insulator (DGSOI) devices, in the calculation of both charge distribution and of electron mobility. We find that the image and exchange correlation potentials produce a greater confinement of the carriers and, according to the uncertainty principle, a greater phonon scattering rate, which produces a decrease in electron mobility. We have also observed that the influence of image and exchange-correlation potentials on electron mobility, while almost negligible for bulk silicon inversion layers, becomes increasingly important as the silicon thickness decreases, due to the effect of volume inversion in DGSOI inversion layers. It is thus essential to take these effects into account in order to correctly evaluate the inversion charge distribution and the electron mobility in DGSOI inversion layers.

A comprehensive study of velocity overshoot effects in double gate silicon on insulator transistors

A comprehensive study of velocity overshoot in double gate silicon on insulator (DGSOI) transistors has been undertaken. Monte Carlo simulations were performed to clarify the dependence of velocity overshoot effects on the low field mobility, channel inversion charge and silicon layer thickness. The relationships and dependences between the energy- and momentum-relaxation times were also investigated. In general, two opposite effects influence electron transport in DGSOI inversion layers as the silicon thickness is reduced: a reduction in the conduction effective mass and a phonon scattering increase. However, we show that electron mobility is mainly determined by the increase in the phonon scattering rate as the silicon thickness is reduced, i.e., the lower the silicon thickness the lower the electron mobility, while the velocity overshoot effects for ultrathin DGSOI inversion layers are dominated by the reduction of the average conduction effective mass, i.e., the lower the silicon thickness the higher the velocity overshoot peak.