Double-gate Silicon-on-insulator MOSFETs Research Articles

Analysis of Lanthanum Oxide Based Double-Gate SOI MOSFET using Monte-Carlo Process.

This work proposes a Double-Gate (DG) MOSFET with a Single Material made of Silicon On-Insulator (SOI). The Lanthanum Oxide material with a high k-dielectric constant has been used as an interface between two gates and the channel. The Monte Carlo analysis has been used to determine the Conduction Band Energy (Ec) profiles and electron sheet carrier densities (ns) for a Silicon channel thickness (tsi) of 10 nm at 0.5 V gate drain-source voltages. The transverse electric fields are weak at the midchannel of DG SOI MOSFETs, where quantum effects are encountered. The Monte Carlo simulation has been confirmed to be effective for high-energy transport. A particle description reproduces the granularity property of the transport for nanoscale modeling. This work utilizes a Monte Carlo (MC) Simulation for the proposed Double Gate Single Material Silicon On Insulator MOSFET with (La2O3=2 nm) as dielectric oxide on upper and lower gate material. The electrical properties of the DG SOI MOSFETs with Lanthanum Oxide were analyzed using Monte Carlo simulation, including the conduction band energy, electric field, potential distribution, particle movement, and average velocity. The peak electric field (E) simulation results and an average drift velocity (υavg) of 6Í105 V/cm and 1.6Í107 cm/s were obtained, respectively. The conduction band energy for the operating region of the source has been observed to be 4 % to the drain side, which obtained a value of -0.04 eV at the terminal end. This proposed patent design, such as double-gate SOI-based devices, is the best suggestion for significant scalability challenges. Emerging technologies reach the typical DG SOI MOSFET's threshold performance when their geometrical dimensions are in the nanometer region. This device based on nanomaterial compounds has been more submissive than conventional devices. The nanomaterials usage in the design is more suitable for downscaling and reducing packaging density.

Nonequilibrium Green's function treatment of a new nanoscale dual-material double-gate MOSFET

In this paper the electrical characteristics of a novel nanoscale double-gate (DG) silicon-on-insulator(SOI) MOSFET, in which the front gate consists of two materials with different work functions, have been investigated by a full quantum-mechanical simulation. The simulations have been done by the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The quantum simulation results show that the new structure decreases significantly the leakage current and drain conductance and increases the on–off current ratio and voltage gain as compared to the conventional DG SOI MOSFET. In this new structure, the potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain, resulting in suppressed short-channel effects like the drain-induced barrier lowering (DIBL) and hot-carrier effect.

Phonon-Limited Electron Mobility Behavior and Inherent Mobility Reduction Mechanism of Ultrathin Silicon-on-Insulator Layer with (111) Surface and Ultrathin Germanium-on-Insulator Layer with (001) Surface

One-dimensional self-consistent calculations and relaxation time approximations are used to study the phonon-limited electron mobility behavior of the inversion layer at room temperature for ultrathin body Si(111) and Ge(001) layers in single-gate (SG) and double-gate (DG) silicon-on-insulator (SOI) and germanium-on-insulator (GOI) metal–oxide–semiconductor (MOS) field-effect transistors (FETs). Assuming a 5-nm-thick SOI layer, it is shown that intravalley phonon scattering (acoustic-phonon scattering) in the DG SOI MOSFET inversion layer is strongly suppressed within a range of medium and high effective field (Eeff) values; DG SOI MOSFETs have higher phonon-limited electron mobility than SG SOI MOSFETs. Many simulations strongly indicate that, for medium Eeff values, the suppression of acoustic-phonon scattering in a 5-nm-thick DG SOI MOSFET primarily stems from the reduction of the form factor (F00) value. Although similar phenomena are observed in approximately 7-nm-thick GOI layers with a Ge(001) surface, it is shown that there is little merit in using the Ge(001) surface for DG GOI MOSFETs.

Features of phonon-limited electron mobility behavior of double-gate field-effect transistor with (111) Si surface channel

One-dimensional self-consistent calculations and relaxation time approximations are used to study the phonon-limited electron mobility of the inversion layer at room temperature for ultrathin body Si (111) layers in single-gate (SG) and double-gate (DG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFET’s). Assuming a 5-nm-thick SOI layer, it is shown that intravalley phonon scattering (acoustic-phonon scattering) in the DG SOI MOSFET inversion layer is strongly suppressed within a range of medium effective field (Eeff) values; DG SOI MOSFETs have higher phonon-limited electron mobility than SG SOI MOSFET’s. Many simulations strongly suggest that the suppression of acoustic-phonon scattering in a 5nm TSOI DG SOI MOSFET primarily stems from the reduction of the form factor (F00) value within medium Eeff values.

A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs

In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET—Two-Dimensional Analytical Modeling and Simulation

In this paper, we present the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, i.e., a dual-material double-gate (DMDG) SOI MOSFET, exhibits significantly reduced short-channel effects (SCEs) when compared with the DG SOI MOSFET. SCEs in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage, and drain-induced barrier lowering. A model for the drain current, transconductance, drain conductance, and voltage gain is also discussed. It is seen that SCEs in this structure are suppressed because of the perceivable step in the surface-potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

An improved semi-classical Monte-Carlo approach for nano-scale MOSFET simulation

A conventional Monte-Carlo simulator has been extended to include electrostatic and transport effects that are most relevant for the analysis of nano-scale MOSFETs with either bulk or single and double gate silicon-on-insulator (SOI) architectures and silicon film thickness down to approximately 10 nm. Corrections to the self-consistent electrostatic potential and a new model for the surface roughness scattering have been included. The effectiveness of the approach has been tested simulating carrier transport in a 25 nm double gate SOI MOSFET. The simulation results point out the strong influence of the scattering on the ON current even in these ultra-scaled devices.

Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications

An analytical model is developed for laterally asymmetric channel (graded channel (GC)) design in double gate (DG) silicon-on-insulator (SOI) MOSFETs. Based on modeling, 2D simulation and experimental results, we show DG MOSFETs with laterally asymmetric channel engineering can achieve high values of saturation drain current, exceptionally high values of Early voltage (>1600 V) and intrinsic DC gain of 70–80 dB for L eff=1.64 μm, well in excess of those reported so far. Results of GC DG MOSFETs have also been compared with experimental and simulated data of uniformly doped double and single gate (SG) SOI MOSFETs. The analysis takes into account the effect of length and doping of the high and low doped regions to develop a compact model suitable for device design. The results of analytical model agree well with experimental and simulation data. We propose design guidelines for overall optimum performance of GC DG MOSFETs for realizing future high performance analog circuits.

Hall effect measurements in double-gate SOI MOSFETs

The electron mobility and concentration in double-gate silicon-on-insulator (SOI) gate-all-around transistors is extracted by Hall effect measurements at room and liquid nitrogen temperature. The Hall mobility is compared with the drift mobility determined from the transconductance measurement of the devices in strong inversion. The results of this study indicate that the method based on I D/( g m) 0.5 provides acceptable values for the drift mobility. The experiment reveals high carrier mobility dominated at room temperature by a phonons scattering mechanism and at low temperature by mixed scattering processes, with a predominance of the surface roughness scattering mechanism. No evidence was found for special transport mechanisms induced by volume inversion in relatively thick SOI films.

Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices

Comparative analysis of the minimum surface potential (Φ m) and the respective position (or location of barrier peaks (y 0)) in various Si MOSFET devices including bulk Si MOSFETs, silicon-on-insulator (SOI) MOSFETs and double-gate SOI MOSFETs has been investigated. For all these three devices we use the same methodology and models to find Φ m and y 0. The analytical results from the three models are utilized to compare and analyse performance of the related devices. The effects of three main important parameters affecting the Φ m and y 0, namely channel length (or L g), drain bias (V d) and gate bias (V g), are discussed. The main motivation of this paper is to show by comparing the model results how the performance of each device is affected by various changes in physical and electrical parameters. These issues have been elaborately investigated in this work. The short-channel effects including drain induced barrier lowering and threshold voltage roll-off (ΔV th) are described and their relationship with Φ m is given.

An equivalent electric-field approximation for formulating sheet density of induced electrons in a silicon layer of symmetric and asymmetric double-gate SOI MOSFETs

An analytical expression for the sheet density of induced electrons in channels of symmetric and asymmetric double-gate (DG) silicon-on-insulator (SOI) MOSFETs in a subthreshold region has been developed. A new approach for approximating the vertical electric-field in the silicon layer enabled the simple expression for electron density to be derived. This model was found to be useful for devices with wide ranges of silicon-layer thickness and channel-impurity concentration.

Modelling of transconductance-to-current ratio (gm/ID) analysis on double-gate SOI MOSFETs

A new design methodology based on the surface potential approach of finding transconductance-to-current ratio (gm/ID) and body factor n of fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) MOSFETs is proposed and their effects on physical as well as electrical parameters are studied and analysed. The methodology is intended for low-power analogue and digital circuits where the weak as well as moderate inversion regions are often used because they provide a good compromise between speed and power consumption. The dependence of gm/ID as well as of their corresponding body factor on temperature is described. The gm/ID ratio indeed is a universal characteristic of all transistors formed by the same process. The study shows that DG SOI MOSFETs have a higher gm/ID ratio and also better body factor values than bulk as well as FD SOI MOSFETs. The present device is a well-suited candidate for the construction of a DG SOI micropower operational transconductance amplifier. This model equation is used to study the influence of various device parameters on gm/ID and their corresponding n. Because the model is quite simple and accurate, it is easy to implement in circuits as well as device simulators.

Semiconductor thickness effects in the double-gate SOI MOSFET

Influence of the semiconductor film thickness in the double-gate silicon on-insulator (SOI) MOSFET on the electron concentration distribution, electron charge density, threshold voltage, electron effective mobility, and drain current is theoretically analyzed. The consideration of the semiconductor region is based on two descriptions: the "classical" model based on a solution to the Poisson equation and the "quantum" model based on a self-consistent solution to the Schrodinger and Poisson equation system. The electron effective mobility and the drain current are calculated with the use of the local mobility model.