We have developed an optical proximity effect correction (OPC) flow for both, the repetitive memory cell patterns by a simulation-based method and for the random logic application specific IC (ASIC) patterns by a rule-based method. Application results for a 0.28 µm static random access memory (SRAM) cell and 0.25 µm ASIC devices have shown that correction time and final data size were feasible for conventional layout design flow and mask fabrication. Also, our system has achieved significant improvement with respect to pattern printing fidelity between designed and printed resist patterns. In addition to this, an automatic alternative phase shift mask (PSM) pattern layout tool has been developed. Using the tool with a double exposure method, 0.16 µm gate patterns for both logic and dynamic random access memory (DRAM) have been obtained with a positive photoresist. The developed lithography computer aided design (CAD) technology has improved the accuracy of pattern formation for state of the art device fabrication. The fabricated patterns have satisfied the required linewidth accuracy, within ±10% of the design value, ones under the practical exposure-focus window.
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