Double-diffused Metal Oxide Semiconductor Research Articles

Investigations of SiC lateral MOSFET with high-k and equivalent variable lateral doping techniques

In this article, a novel high-k and equivalent variable lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and calibrated by numerical simulation. The three-dimensional equivalently P-top region is employed in the drift region, and only one additional ion implantation step is needed to achieve variable lateral doping (VLD) technique. The VLD technique combined with the high-k dielectric in the drift region, not only increases the doping concentration of N-drift region, but also optimizes the electric field distribution in the drift region. Simulation results indicates that the BV, specific on-resistance and the short-circuit withstand time of the proposed Hk VLD LDMOS are improved by 48.91%, 53.6% and 60.2% respectively, compared with those of the conventional LDMOS device.

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

In this paper, a novel double-gate trench silicon-on-insulator lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with double-dielectric material (DGDK-LDMOS) is proposed. DGDK-LDMOS has two dielectric materials: a reverse-L-shaped high-k (HK) thin film and an low-k (LK) buried oxide layer. The HK thin film optimizes the electric field distribution on the drift region surface, attracting electric flux, and the excellent withstand voltage of the LK buried oxide layer can significantly improve the breakdown voltage (BV) and reduce specific on-resistance (R on,sp) of the device. The modulation mechanism of LDMOS by HK thin film and LK buried oxide layer is analyzed. The results show that compared with conventional LDMOS, when the permittivity of HK thin film is 25 and the permittivity of LK buried oxide is 3, the BV of DGDK-LDMOS is increased by 89.6%, the R on,sp is decreased by 26.4%, and the figure of merit (FOM, FOM = BV2/R on,sp) is increased by 397.2% from 3.6 MW cm−2 to 17.9 MW cm−2. Meanwhile, the output characteristics, transfer characteristics, lattice temperature, AC characteristics and switching characteristics of DGDK-LDMOS are also discussed and compared.

In0.53Ga0.47As/In0.52Al0.48As Quantum Well Step Gate LDMOS to Improve the Device Performance

In this work, a new laterally double diffused metal oxide semiconductor (LDMOS) using In0.53Ga0.47As/In0.52Al0.48As Quantum well (QW) layer with a p-well step gate has been proposed. In the proposed device structure, the gate region splits into three steps in which the oxide thickness increases from the source to the drain end. As the gate insulator width varies from source to drain end, it results in better control of the gate over the channel and also a reduction in the gate-to-drain capacitance (CGD). These features offer higher transconductance with reduced switching delays, which makes the device appropriate for RF applications. Again, the concentration of current in the channel section is enhanced due to the presence of the Quantum well region and the InP spacer layer, which drastically reduces the On-resistance. But, the device achieves lesser gate-to-drain capacitance which results in decrease in the switching speed. On the other hand the proposed device offers less gate charge with the low value of CGD gives minimised switching loss. Based on 2D TCAD simulation, the proposed QW LDMOS exhibits 70% improvement in On-resistance, 45% in breakdown voltage, 84% improvement in peak transconductance, 26% improvement in switching delay, and 19% improvement in gate charge density as compared to conventional In0.53Ga0.47As devices.

Temperature Reliability Investigation for a 400 W Solid-State Power Amplifier under High and Cold Conditions

In order to study the temperature reliability of high-power amplifiers under high cand cold conditions, a 400 W solid-state power amplifier was taken as an example to explore the variation in its performance. The test results showed that its output power, gain, and power-added efficiency increased with the increase in temperature at a fixed frequency. Under a fixed input power, Pout and gain both showed different trends with the rising temperature. Within the frequency band of 2–10 MHz, the higher the temperature, the better the output power and gain. However, within the frequency range of 10–30 MHz, the higher the temperature, the worse the performance. Moreover, with the increasing temperature, its power-added efficiency, the second harmonic and the third harmonic also showed a decreasing trend. Detailed analysis showed that the degradation and inversion of performance parameters are closely related to the zero temperature coefficient and self-heating effect of the lateral double-diffused metal–oxide–semiconductor field-effect transistor. Meanwhile, it is also affected by the circuit structure and thermal design of the PA. In order to ensure stable performance in different environments, performance degradation can be improved by hardware compensation. Therefore, analyzing the working parameters at different temperatures for high-power PAs is the key to achieving temperature control and ensuring their long-term stability and reliability. This can provide relatively accurate reference data for subsequent heat dissipation optimization, greatly improve design efficiency, and even shorten the development cycle and reduce costs.

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

A novel stepped L-shaped trench gate silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with N-pillar (SLTGN-LDMOS) is proposed. SLTGN-LDMOS contains a highly doped N-pillar, assisting in reducing the specific on-resistance (R on,sp). The stepped L-shaped trench gate (SLTG) attracts electrons to attach to the edge of the trench, thus directing more current to flow along the edge, which decreases R on,sp effectively. Furthermore, new electric field peaks are generated on the surface of the drift region, thus increasing the breakdown voltage (BV). As a result, compared with the conventional structure (C-LDMOS), the BV of SLTGN-LDMOS increases from 63 V to 162.7 V, and the R on,sp decreases from 1.85 mΩ·cm2 to 1.46 mΩ·cm2. Then, the figure of merit (FOM1, BV2 /R on.sp) increases remarkably from 2.15 MW·cm−2 to 18.13 MW·cm−2. In addition, the maximum surface temperature of SLTGN-LDMOS is 395.3 K, slightly lower than the 398.7 K of C-LDMOS.

SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

The silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) with high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{k}$</tex-math> </inline-formula> multi-fingers (HKMFs) is proposed and investigated. The fingertips are distributed at specific locations to modulate the electric field distributions and improve the device performances. First, the electric field peaks formed at the fingertips could optimize the electric field distributions, which improves the breakdown voltage (BV) of the LDMOS effectively. Meanwhile, the multi-fingers are embedded into the drift region to increase the optimal drift doping concentration, which facilitates the positive conduction of the device and reduces the specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{on,\text{sp}}}\text{)}$</tex-math> </inline-formula> . The simulation results show that the proposed HKMF-LDMOS with five multi-fingers increases the BV by 59.2%, reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{on,\text{sp}}}$</tex-math> </inline-formula> by 37.8%, and improves the figure of merit (FOM) by 4.07 times when compared to the conventional LDMOS.

Novel SenseFET structure for VDMOS with adopting body reverse bias technique to adjust the reference current ratio

- Detecting current accurately and low-loss is an extremely important and challenging task in intelligent power switches. In the paper, the novel SenseFET structure, based on the Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) is proposed, which realizes variable reference current ratios by employing the body reverse bias technique. Several simulations are carried out, by using Sentaurus TCAD Software, to ensure that other performances of the sense transistor, with body reverse bias, are not affected. Compared to the constant reference current ratio, the new method improves the current sensing accuracy by 14% at 0.1 A, makes it easier to extract the targeted voltage by using a small reference current ratio at small load currents and reduces the power dissipation of the detection branch by using a large reference current ratio at large load currents. The structure, presented in this paper, provides the guiding methodology for a wide range of load current sensing and can be easily fabricated without adding additional mask.

Study of TID radiation effects on the breakdown voltage of buried P-pillar SOI LDMOSFETs with P-top region

This article presents the numerical investigation on the total ionizing dose (TID) radiation induced breakdown voltage shifting behavior of the silicon-on-insulator (SOI) buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) with a P-top region (TP). We validate the employed simulation models and structure parameters by the experiments of the 200 V rated SOI BP-LDMOS devices. We also discuss the breakdown voltage (BV) analysis of the SOI BPTP-LDMOS under different doping concentrations in the drift region. Because the lateral breakdown voltage can be effectively enhanced by the P-top region under STI layer, the SOI BPTP-LDMOS behaves a wider Nd window for rated 200 V compared with the SOI BP-LDMOS. Finally, we perform the numerical investigation of the TID radiation effect on the BV shift. Using the TID hardening design with the electric field modulation method, the hardened BPTP-LDMOS can achieve a significant improvement in the TID tolerance compared with the hardened SOI BP-LDMOS, from 575 to 775 krad(Si).

A novel optimum variation lateral doping SiC lateral double-diffused metal oxide semiconductor with improved performance

In thsi paper a novel optimum variation lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and numerically simulated. For the proposed 4H-SiC LDMOS, an optimized three-stage variation of lateral doping (VLD) p-top layer is employed in the drift region; thus the doping concentration of the n-drift region can be significantly increased, resulting an ultra-low specific resistance (R on,sp). The breakdown voltage (BV) is also improved, since the electric field distribution of the drift region is optimized. The current saturation characteristic, gate–drain capacitance (C GD) and gate-to-drain charge (Q gd) of the proposed device are all improved, thanks to the effect of the source-connected p-top region. Compared with a conventional LDMOS, the numerical simulation results show that the BV, R on,sp and Q gd of the proposed LDMOS are improved by more than 11.9%, 47.3% and 46.3%, respectively. The three-dimensional simulation result indicates that the entire three-stage p-top VLD layer can be produced by one-time fabrication process, which brings great convenience to future production.

Response of Commercial P-Channel Power VDMOS Transistors to Ionizing Irradiation and Bias Temperature Stress

In this paper, the effects of successively applied static/pulsed negative bias temperature (NBT) stress and irradiation on commercial p-channel power vertical double-diffused metal-oxide semiconductor (VDMOS) transistors are investigated. To further illustrate the impacts of these stresses on the power devices, the relative contributions of gate oxide charge ([Formula: see text]) and interface traps ([Formula: see text]) to threshold voltage shifts are shown and studied. It was shown that when irradiation without gate voltage is used, the duration of the pre-irradiation static NBT stress has a slightly larger effect on the radiation response of power VDMOS transistors. Regarding the fact that the investigated components are more likely to function in the dynamic mode than the static mode in practice, additional analysis was focused on the results obtained during the pulsed NBT stress after irradiation. For the components subjected to the pulsed NBT stress after the irradiation, the effects of [Formula: see text] neutralization and [Formula: see text] passivation (usually related to annealing) are more enhanced than the components subjected to the static NBT stress, because only a high temperature is applied during the pulse-off state. It was observed that in devices previously irradiated with gate voltage applied, the decrease of threshold voltage shift is significantly greater during the pulsed NBT stress than during the static NBT stress.

Phase Change Memories in Smart Sensing Solutions for Structural Health Monitoring

Smart devices for structural health monitoring provide edge computing capabilities to reduce wireless transmission and, thus, power consumption. Although effective algorithms have been proposed in the last few decades, traditional microcontrollers require heavy data flow between the memory and the central processing unit that involves a considerable fraction of the total energy consumption. Phase change memory has recently emerged as an attractive solution in the field of resistive nonvolatile memory for analog in-memory computing, which is a valid approach to avoid data being conveyed among distinct elaboration units. However, it has never been envisaged in structural health monitoring applications. As this technology is still in an embryonic state, several challenges related to nonlinearities and nonidealities of the memory elements and the energy expenditure related to the memory reprogramming process may undermine its usage. In this paper, the application of a novel identification approach for civil infrastructures is investigated using phase change memories. The main computational core of the presented algorithm, consisting of one-dimensional convolutions, is particularly suitable for implementations involving analog in-memory computing, thus showing the great potential of this technology for structural health monitoring applications. The test unit is an embedded phase change memory provided by STMicroelectronics and designed in 90-nm smart power bipolar complementary metal-oxide-semiconductor (CMOS)-double-diffused metal-oxide-semiconductor (DMOS) technology with a Ge-rich Ge-Sb-Te alloy for automotive applications. Experimental results obtained for a viaduct of an Italian motorway support the efficacy of the method. Moreover, the influence of nonidealities on the outcomes of damage identification based on both dynamic and quasi-static structural parameters is examined.

Novel Si/SiC heterojunction lateral double-diffused metal oxide semiconductor field effect transistor with low specific on-resistance by super junction layer

A novel Si/SiC heterojunction lateral double-diffused metal oxide semiconductor (LDMOS) field effect transistor with the low specific on-resistance (Ron,sp) by super-junction (SJ) layer (Si/SiC SJ-LDMOS) is proposed in this paper. On the basis of using N-Buffer layer to solve substrate assisted depletion effect (SAD), breakdown point transfer terminal technology (BPT) is realized by the deep drain structure of Si/SiC heterojunction and electric field modulation is carried out, which further improves the breakdown voltage (BV) of Si/SiC SJ-LDMOS, alleviates the contradictory relationship between the BV and the Ron,sp. Through ISE TCAD simulation, the result shows that with the same drift region length of 20 μm, the BV is increased from 114 V of conventional SJ-LDMOS (Cov. SJ-LDMOS) and 270 V of SJ-LDMOS with N-Buffer layer (Buffer SJ-LDMOS) to 374 V of Si/SiC SJ-LDMOS, increased by 228% and 38%, respectively. In addition, the Ron,sp of Cov. SJ-LDMOS, Buffer SJ-LDMOS and Si/SiC SJ-LDMOS are 46.26 mΩ cm2, 26.96 mΩ cm2 and 25.85 mΩ cm2, respectively. Moreover, the figure-of-merit (FOM) of proposed Si/SiC SJ-LDMOS device is 5.411 MW/cm2, which means the Si/SiC SJ-LDMOS has a better performance to break the silicon limit. The influence of design parameters on device performance is also discussed.

A novel SOI-LDMOS with field plate auxiliary doping layer that has improved breakdown voltage

Field plate (FP) is a widely used electric field optimization technique in lateral power devices. However, we found that the electric field distribution optimized by FP still has poor uniformity due to the excessive induced charges at the end of FP. To solve the problem, a novel silicon on insulator based lateral double diffused metal oxide semiconductor (SOI-LDMOS) with a field plate auxiliary doping layer (FPADL) is proposed. Our investigation proved that the FPADL introduces an additional part of space charge and partially balances the excessive induced charges at the end of FP. As a result, the FPADL introduces an additional electric field peak and improves the electric field distribution. Thereby, the SOI-LDMOS with FPADL has improved breakdown voltage (BV). The effect of FPADL is verified experimentally. In our experiment, the FPADL is realized by modifying the mask of buffer layer to avoid increasing the process cost. The measurement results showed that, comparing with the conventional SOI-LDMOS with FP, the proposed SOI-LDMOS with FPADL improved the BV by 9.52% with the on-resistance and the process cost maintained. Therefore, the proposed SOI-LDMOS with FPADL is a promising device.

Design considerations of a novel Triple Oxide Trench Deep Gate LDMOS to improve self‐heating effect and breakdown voltage

In this study, design considerations of a new device structure are presented to improve the self-heating effect (SHE) and the breakdown voltage of the Deep Gate LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) transistor and compared with a conventional LDMOS (C-LDMOS). In this case, triple oxide trenches with an N+ trench are embedded in the drift region. These trenches create additional peaks in the electric field profile, so the electric field is modified. The authors demonstrate that by optimising the trenches, the breakdown voltage of the device increases. Also, a partially buried oxide is used in the proposed structure to create a conduction path that significantly reduces the SHE. Moreover, the results indicate that the specific on-resistance, lattice temperature, and breakdown voltage of the proposed device are improved considerably compared to the C-LDMOS.

Mechanism and solution of sharp defects in trench double-diffused metal-oxide semiconductor polysilicon recess etching

The sharp defects were observed in the center of the trench during trench double-diffused metal-oxide semiconductor polysilicon recess etching using HBr and He-O2 gas plasma. To understand this phenomenon, external controllable parameters such as pressure and etch gas were used to study the changes in the morphology of polysilicon in over etching. The result shows that there are two key factors for the generation of sharp defects, one is the gap left by incomplete polysilicon filling in the trench and the other is the flow rate of He-O2 in over etching. Component analysis shows that the main components of defects are Si and O. Hence, the theory of sidewall oxidation is proposed to explain the generation of oxide, and the accuracy of the theory was also confirmed by subsequent orthogonal experiments. Finally, a solution to this kind of defect problem is proposed, that is, to reduce the flow of He-O2 to eliminate the generation of defect.

Novel Vertical Power MOSFET With Step Hk Insulator Close to Super Junction Limit Relationship Between Breakdown Voltage and Specific ON-Resistance by Improving Electric Field Modulation

A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> (Hk) MOSFET concept in this article with the step high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation effect of step Hk insulator, which decreases the specific on-resistance of step Hk VDMOS compared to the conventional Hk VDMOS. The various thickness of the Hk insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of the step Hk VDMOS. Meanwhile, an analytical model for novel step Hk VDMOS is obtained by solving the 2-D Poisson equation in an N-type drift region, and the 2-D Laplace equation in the step Hk region, which can reasonably explain the modulation effect of the step Hk region on the electric field distribution. The results show that the BV of the step Hk VDMOS is increased from 639 V of the conventional Hk VDMOS to 736 V with the same drift length of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42~\mu \text{m}$ </tex-math></inline-formula> . The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.

Study of TID Radiation Effects on the Breakdown Voltage of Buried P-Pillar SOI LDMOSFETs

This paper presents experimental and numerical analysis of a buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) fabricated on a silicon-on-insulator (SOI) substrate. The experimental results indicate that the specific on-resistance ( R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> on,sp</sub> ) of the SOI BP-LDMOS is 9.5 mΩ· cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a breakdown voltage (BV) of 229 V, which corresponds to a figure of merit (FOM) of 5.52 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The analysis of structural parameter optimization of the SOI BP-LDMOS under different doping concentrations in the drift region and P-pillar layer is conducted via numerical simulation. The results show that the tested sample can achieve about 80% of the maximal FOM. Finally, the experimental and numerical investigation of the total ionizing dose (TID) radiation effect on the BV shift is performed. The TID tolerance of the measured SOI BP-LDMOS can reach 300 krad(Si) to support a voltage of 200 V. Due to the electric field modulation hardening design, compared with the conventional hardened SOI LDMOS, the studied hardened BP-LDMOS can achieve a significant improvement in the TID tolerance from 225 krad(Si) to 525 krad(Si).

PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control

This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and automatic gain control. The PLL consisting of a phase frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO) makes the driving frequency to be locked at the resonant frequency. The resonator is modeled by Butterworth–Van Dyke equivalent circuit model with motional resistance of 72.8 kΩ, capacitance of 6.19 fF, inductance of 79.4 mH, and parasitic parallel capacitance of 2.59 pF. To mitigate the magnitude and phase distortion in the resonator frequency response, it is necessary to compensate for the parasitic capacitance. The proposed automatic parasitic capacitance cancellation loop is operated in the open-loop mode. In the automatic parasitic capacitance cancellation phase, the outputs of the transimpedance amplifier (TIA) at the lower and higher frequency than the resonant frequency (VH and VL), are compared, and the programmable compensation capacitor array matches the VH and VL using binary-searched algorithm to cancel the parallel parasitic capacitance. The automatic gain control (AGC) loop keeps the oscillation at the suitable amplitude, and the AGC output can be used as a measurement of the motional resistance. The AGC loop is also digitally controlled. The proposed resonator driving IC is designed in a 0.18-μm bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm2. The simulated phase noise is −61.1 dBc/Hz at 1 kHz and the quality factor ( Q-factor) is 59,590.

Deep neural network-based approach for breakdown voltage and specific on-resistance prediction of SOI LDMOS with field plate

Breakdown voltage (BV) and specific on-resistance (R on,sp), are critical indicators to measure the quality of the power device. To improve the device performance, field plate technology has been developed by modifying the electric field distribution. However, the current technology computer-aided design (TCAD) simulation cannot predict the effect of field plate on BV and R on,sp simultaneously, and the operation process is complicated. This paper proposes a deep neural network (DNN)-based model instead of TCAD to predict the effect of field plates on BV and R on,sp of silicon on insulator lateral double diffused metal oxide semiconductor. The experimental results show that, compared with TCAD simulation, the average deviation for BV and R on,sp is 5.06% and 2.55%, respectively. Also, the time for BV prediction is accelerated significantly up by 1.23 × 105. Our DNN model provides a potential direction to predict device performance with higher efficiency.

Capacitance–Voltage Technique Based on Time Varying Magnetic Field for VDMOSFET—Part II: Measurements and Parameter Extractions

In part I, we have proposed a new capacitance–voltage technique ${C}$ ( ${V}$ ), which is simultaneously based on external ac magnetic field for surface potential modulation and on dc voltage to sweep the gate voltage. In part II, we describe the parameter extractions of vertical double diffusion metal–oxide–semiconductor field effect transistor (VDMOSFET) devices, combining the capacitance characteristics of gate–source, ${C}_{\text {GS}}$ ( ${V}_{G}$ ) and gate–drain ${C}_{\text {GD}}$ ( ${V}_{G}$ ), measured using the above cited technique, with those measured conventionally. In doing so, we have been able to extract semiconductor capacitance ( ${C}_{\text {SC}}$ ), interface trap capacitance ( ${C}_{\text {it}}$ ), doping profile concentration ${N}$ ( ${x}$ ), and interface trap density ${D}_{\text {it}}$ ( ${E}$ ) of different regions of VDMOSFET.