Double-diffused Metal Oxide Semiconductor Research Articles

Designing ESD Protection Devices for Ultrafast Overvoltage Events

This article provides an understanding of the transient voltage overshoot physics observed with electro-static discharge (ESD) n-type, p-type, and n-type diffusions (NPN) bipolar devices through the use of calibrated technical computer-aided design (TCAD) with measured silicon results. This analysis graphically steps through each stage of the measured transient electrical response, to explain the inertia that limits the speed of the NPN ESD cell, and then uses this knowledge to provide a fully characterized silicon solution for ultrafast ESD events to achieve an 8-kV IEC61000-4-4 rating. This solution is developed by exploring five different integrated designs that are constructed on an 80-V bipolar and complimentary double-diffused metal-oxide semiconductor (BiCDMOS) process platform to protect against a product level 125-V voltage overshoot gate oxide ruptures as measured with a 0.6-ns rise time transmission line pulse (TLP). The fully characterized electrical results for each test overshoot structure with a fixed layout area of $200\,\,\mu \text{m}\,\,\times200\,\,\mu \text{m}$ , are in parallel to NPN ESD cells arranged with two in series and two in parallel ( $200\,\,\mu \text{m}\,\,\times 80\,\,\mu \text{m}$ ) and compared in terms of the current-carrying capability before the gate oxide rupture voltage of 125 V is reached. The results show that a diode engineered with a vertical breakdown achieves an ESD strength of 9.7 A before the overshoot voltage reaches the target of 125-V, resulting in a net 0.17 mA $\mu \text{m}^{-{2}}$ . The combined use of this vertical diode structure in parallel to the NPN ESD cell translates into a 7-A improvement in the strength of a conventional NPN for ultrafast timescales, which achieves the 8-kV International Electrotechnical Commission (IEC) ESD performance for this case study.

Displacement damage on P-channel VDMOS caused by different energy protons

In this paper, characteristics of displacement and ionization damage on P-channel VDMOS (Vertical double-diffused Metal Oxide Semiconductor) deceives caused by 3 MeV and 6 MeV protons were investigated. The key electrical parameters such as threshold voltage and leakage current are measured. Experimental results show that threshold voltage move to left shift and the leakage current increases. The electrical properties measurement is performed in-situ by 3 MeV and 6 MeV protons, and the changes of electrical properties are different. The shift of threshold voltage is higher for the 6 MeV protons than for the 3 MeV ones. The leakage current is higher after the irradiation by 3 MeV protons than it by the 6 MeV ones. Annealing at room temperature for 300 days leads to an obvious decrease in the shift of threshold voltage, and has a little effect on leakage current. The increase in leakage current is mainly caused by displacement and the ionization damage mainly changes the shift of threshold voltage.

A Lateral Double-Diffusion Metal Oxide Semiconductor Device with a Gradient Charge Compensation Layer

In order to better shield the substrate-assisted depletion (SAD) effect and improve the breakdown voltage of super-junction (SJ) devices, an SJ lateral double-diffusion metal oxide semiconductor device with a gradient charge compensation layer (gradient device) is proposed. The main feature of this structure is to introduce a gradient charge compensation layer between the SJ layer of a conventional device and the substrate. The depth of the gradient charge compensation layer increases gradually from the source to the drain. The charge distribution in the drift region is optimized by reducing the compensation charge on the side near the source and increasing the compensation charge on the side near the drain. Introduction of the layer improves shielding of the SAD effect, and the electric field on the surface of the structure is an approximately rectangular distribution, thus the breakdown voltage is improved. The simulation results show that the gradient device has 409-V breakdown voltage and a 9.5-MW cm−2 figure of merit with a drift region length of 21 μm. Compared with the conventional SJ structure (conventional device) with the same drift length, the breakdown voltage and figure of merit of the gradient device are increased by 57.3% and 137.5%, respectively.

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

A novel silicon (Si) on silicon carbide (SiC) lateral double-diffused metal oxide semiconductor field effect transistor with deep drain region is proposed. Its main idea is transferring the breakdown point and utilising the high critical electric field of SiC material to suppress the curvature effect of the drain, which eventually alleviates the trade-off relationship between breakdown voltage (BV) and specific on-resistance ( R on,sp ). Through the TCAD simulation, the results show that the BV is significantly improved from 240 V for conventional Si lateral double-diffused metal oxide semiconductor (LDMOS) to 384 V for the proposed structure with the drift region length of 20 μm, increased by 60%. The figure-of-merit of the conventional Si LDMOS and the Si/SiC LDMOS are 2.04 and 4.26 MW/cm 2 , respectively. It indicates that the proposed structure has better performance than the Si counterpart. The influences of design parameters and interfacial charges on the device performance are also discussed in this work.

A Novel High Voltage Ultra-Thin SOI-LDMOS With Sectional Linearly Doped Drift Region

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a 0.17 μm SOI layer with a source field plate covering the full drift region. Low specific on-resistance Ron,sp is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> of 960 V with a superior figure of merit (FOM = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) of 5.98 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.

PSJ LDMOS with a VK dielectric layer

A partial super junction lateral double-diffused metal–oxide–semiconductor field-effect transistor with a variable- k dielectric layer (PSJ VK LDMOS) is proposed in this Letter. Low- k material and PSJ are introduced into the device. PSJ provides a low-resistance channel to reduce the specific on-resistance ( R on,sp ). Furthermore, according to an enhanced dielectric layer field, low- k buried layer can sustain the high breakdown voltage (BV). To eliminate substrate-assisted depletion effect and improve the lateral BV of the proposed structure, the charge compensation layer in the device adopts a variation of lateral doping technique and is combined with the N pillar in PSJ. Ultimately, the simulation results show that BV of 795.5 V and the figure of merit (FOM) of 6.1 MW cm −2 are achieved for PSJ VK LDMOS. BV and FOM are enhanced by 71.4 and 81.1%, respectively, compared with con. PSJ SOI LDMOS with the drift region length of 46.5 μm. Furthermore, R on,sp of 103.4 mΩ cm 2 is reduced by 31.2% compared with the ‘silicon limit’ at the same BV class, which breaks the ‘silicon limit’.

A 2–10 MHz GaN HEMTs Half-Bridge Driver With Bandgap Reference Comparator Clamping and Dual Level Shifters for Automotive Applications

Gallium nitride (GaN) high electron mobility transistors (HEMTs) are promising power devices due to their excellent characteristics. However, GaN HEMTs have vulnerable gates that are susceptible to noise and voltage spikes, limiting their implementation in power converters. This paper presents a GaN HEMTs half-bridge driver with bandgap reference comparator clamping (BGRCC) and dual level shifters (DLS) for high switching frequency automotive applications. The BGRCC scheme can adaptively clamp the bootstrap rail voltage at an appropriate level with acceptable voltage ripples, which guarantees the safety of high-side GaN HEMT. Meanwhile, DLS scheme is applied in both the high- and low-side driving path to effectively drive the GaN HEMTs with low propagation delay and high dv / dt immunity. The proposed driver is fabricated in 0.18 μm high voltage bipolar-complementary metaloxide semiconductor (CMOS)-double-diffused metaloxide semiconductor (DMOS) process and can support 2–10 MHz operating. The functionality and performance are verified by experimental results. A buck converter utilizing this driver with GaN HEMTs can achieve maximum efficiency of 91.58% with quite electromagnetic interference behavior in the 16.5-W output power rating when operating at 2 MHz, which is superior to conventional silicon-based power converters and suitable for automotive applications.

Model and Experiments of Small-Size Vertical Devices With Field Plate

A small-size vertical device with field plate is designed and experimentally realized in this paper. The modulation effect of the field plate causes an enhanced bulk electric field (ENBULF) and improves the breakdown voltage ${V}_{\textsf {B}}$ . A 2-D electric field model is developed to give the ENBULF condition corresponding to the maximum ${V}_{\textsf {B}}$ and the optimal specific ON-resistance ${R}_{ \mathrm{ON},\textsf {sp}}$ . Based on the model, the minimum figure of merit (FOM) (gate charge ${Q}_{\textsf {g}}\times \mathrm{\scriptstyle ON}$ -resistance ${R}_{ \mathrm{ON}}$ ) is discussed for a typical ENBULF device, i.e., the shield-gate vertical double diffused metal–oxide–semiconductor (SG-VDMOS). The calculated results are in good agreement with the simulations. Furthermore, a 35-V SG-VDMOS is analytically designed and experimentally implemented, which obtains a ${R}_{ \mathrm{ON},\textsf {sp}}$ of 4.4 $\text{m}\Omega \cdot \textsf {mm}^{2}$ and a gate to drain charge ${Q}_{\textsf {gd}}$ of 11.3 nC, respectively. The experiment realizes the minimal FOM and a ${R}_{ \mathrm{ON},\textsf {sp}}$ reduced by 28.6% when compared with the conventional “silicon limit.”

High-Voltage Lateral Double-Diffused Metal-Oxide Semiconductor with Double Superjunction

A high-voltage lateral double-diffused metal-oxide semiconductor with double superjunction (DSJ LDMOS) is proposed in this paper. A vertical SJ under the drain and a lateral SJ in the drift region are introduced to form a double SJ in the DSJ LDMOS. To suppress the substrate-assisted depletion effect of the lateral SJ, a charge compensation layer linearly doped from source to drain is adopted in the drift region. In off-state, the vertical SJ enhances the depletion of the substrate to improve the vertical breakdown voltage (BV) and modulates the lateral electric field to increase the lateral BV. The lateral SJ increases the lateral BV and modulates the vertical electric field to improve the vertical BV. The vertical SJ is composed of N and P pillars with different concentrations. In on-state, the lateral SJ also provides a low-resistance channel, which decreases the specific on-resistance (Ron,sp). Simulation results indicate that the BV, figure of merit (FOM), and Ron,sp of the DSJ LDMOS are 1138 V, 10.5 MW cm−2, and 103.4 mΩ cm2, respectively. The BV and FOM of the DSJ LDMOS are increased by 31.3% and 483% compared with the conventional vertical SJ LDMOS (Con. VSJ LDMOS), while the Ron,sp of the DSJ LDMOS is reduced by 70%. The “silicon limit” is thus broken by the DSJ LDMOS.

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate**Project supported by the National Natural Science Foundation of China (Grant No. 61464003) and the Guangxi Natural Science Foundation, China (Grant Nos. 2015GXNSFAA139300 and 2018JJA170010).

A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOS) with enhanced depletion effect by surface substrate is proposed (ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches (SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance (Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage (BV). Compared to a conventional LDMOS (C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 mΩ·cm2 to 23.24 mΩ·cm2 and the Baliga’s figure of merit (FOM) of is 9.07 MW/cm2.

The Effect of Shallow Trench Isolation and Sinker on the Performance of Dual-Gate LDMOS Device

In this paper, a dual-gate laterally double-diffused metal–oxide–semiconductor (DG-LDMOS) device with shallow trench isolation (STI) and sinker at the source side has been proposed. STI and sinker help to provide isolation and reduce the leakage current, respectively, in the device. This is an improvement over a single-gate (SG) LDMOS device when only one gate is used and no STI and sinker are there. The study of both the devices has been carried out using the ATLAS SILVACO simulator. In the simulation studies, all the dimensions and doping parameters of both devices have been kept the same except gate length and channel doping. The distance between two gates of DG-LDMOS device has been kept smaller. This has been done to overcome the island and overlapping issues. The simulation studies have shown a significant improvement in DG-LDMOS device parameters in comparison to the SG-LDMOS device. The DG-LDMOS device provides high breakdown voltage, low ON-resistance, high $f_{\sf {T}}$ and $f_{\sf {max}}$ , low drain-induced barrier lowering, and better output conductance as compared to conventional SG-LDMOS device. These features make the DG-LDMOS device an excellent candidate for RF applications.

Numerical Analysis of the LDMOS With Side Triangular Field Plate

A Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) with side triangular field plate (STFP) is proposed for improving the breakdown voltage ( BV ) and reducing the specific on-resistance ( $R_{on,sp}$ ). The main feature of the novel LDMOS is the STFPs at both ends of the drift region, and they are fabricated into the dielectric pillars. With the introduction of the STFPs, the electric field peaks at the P-well/N-drift and N+/N-drift junctions are reduced effectively. The STFPs together with the dielectric pillars modulate the surface and vertical electric field distributions, which enhances the BV . Meanwhile, the doping concentration of the silicon pillars in the drift region is optimized and thus reduces the $R_{on,sp}$ . The simulation results indicate that the BV of 379 V and the $R_{on,sp}$ of 37.3 $\text{m}\Omega \cdot $ cm2 are achieved by the STFP-LDMOS. The figure of merits ( FOM ) of the STFP-LDMOS is 2.7 times compared with the conventional LDMOS without STFPs. The STFP-LDMOS demonstrates a great trade-off between the $R_{on,sp}$ and BV .

Split‐gate LDMOS with double vertical field plates

In this study, a novel split-gate lateral double-diffused metal oxide semiconductor field effect transistor with double vertical field plates (SG DVFP LDMOS) is proposed. The first feature of the SG DVFP LDMOS is that the SG with gradient gate oxide is introduced. The SG not only optimises the bulk electric field distributions to increase the breakdown voltage (BV) but also reduces the gate-drain charge (Q GD) owing to the thick gate oxide. The second feature of the SG DVFP LDMOS is the presence of the DVFP and P-pillar. They modulate the bulk electric field distributions and assist to deplete the drift region. So the specific on-resistance (R on,sp) is decreased and the BV is improved. The source vertical field plate reduces the contact region between the gate and drain, thereby the Q GD is reduced. Compared with the conventional SG LDMOS and rectangle-gate DVFP LDMOS, the figure of merit FOM1 of SG DVFP LDMOS is increased by 123.2 and 86.6%, and the loss figure of merit FOM2 is enhanced to 16.9 and 37.2%. Simultaneously, the key process steps of the SG DVFP LDMOS are proposed.

A simple metal-semiconductor substructure for the advanced thermo-mechanical numerical modeling of the power integrated circuits

The metallization of double-diffused metal-oxide semiconductor (DMOS) power devices, which operate under fast thermal cycling (FTC), undergoes thermal induced plastic metal deformation (TPMD). The design of the metallization has a significant impact on the device lifetime and thus requires a thorough understanding of the temperature, stress and strain distribution. A simple three-dimensional (3D) transistor substructure which is commonly found in various high integration Bipolar-CMOS-DMOS (BCD) technologies is analysed. The thermomechanical behaviour is studied with the finite element method (FEM) for investigation of two potential failure mechanisms: delamination of power metal and accumulation of plastic deformation in signal metallization layer (which leads to inter-metal dielectric cracking). These failure mechanisms are analysed on two versions of the structure: the first one has only signal and power metal lines and the second one has vias, in addition to the signal and power metal lines. The target of the paper is to propose an efficient finite element analysis (FEA) model that can be used for a qualitative assessment of thermo-mechanical phenomena in the metal system of high integration BCD technologies.

Incorporation of hafnium and platinum metal in vertical power MOSFETs

A novel, vertical single-diffused metal–oxide–semiconductor (VSDMOS) structure is proposed by applying workfunction engineering to a vertical power metal–oxide–semiconductor field-effect transistor (MOSFET) with source and drain regions formed using the charge plasma concept. Electron and hole plasma was induced by employing hafnium and platinum metal. Furthermore, the electrical characteristics of the proposed VSDMOS were compared with those of conventional vertical double-diffused metal–oxide–semiconductor devices, revealing that the proposed VSDMOS exhibits a 14 % increase in current driving capability, with improved breakdown voltage.

Source engineering on ruggedness and RF performance of n-channel RFLDMOS

The state-of-art n-channel RFLDMOS (Radio Frequency Lateral Double-diffusion Metal Oxide Semiconductor) FETs with different source engineering have been fabricated using 0.18 μm BCD (Bipolar/COMS/DMOS) process. The ruggedness and RF performance of RFLDMOS have been studied with TLP (Transmission Line Pulse) test, VSWR (Voltage Stop Wave Ratio) test, and source/load-pull test. It was found that PBL (P+ buried layer) source engineering could improve its ruggedness remarkably. The mechanism of this improvement has been studied by introducing equivalent parasitic circuit. The dominant factor is the resistor RB which delays turn-on characteristic of parasitic NPN in equivalent circuit. And the computational model of RB is proposed. Furthermore, the optimal performance of RFLDMOS has also been discussed.

Double trenches LDMOS with trapezoidal gate

A novel double trenches lateral double diffused metal oxide semiconductor with trapezoidal gate (TGDT LDMOS) is proposed. One feature of the device is that two dielectric trenches which are equivalent to two field plates are introduced in the drift region. The two dielectric trenches not only modulate the body electric field to improve the breakdown voltage (BV) of the device but also assist to deplete the drift region to reduce the specific on-resistance ( R on,sp ). The other feature is the presence of the trapezoidal gate which increases the gate oxide thickness to reduce the capacitance of gate and drain ( C GD ). Thereby the charge between the gate and drain ( Q GD ) is reduced, so that the conduction loss of the device is decreased. Compared with the conventional LDMOS with trapezoidal gate and the single trench LDMOS with trapezoidal gate, the figure of merit (FOM = BV 2 / R on,sp ) of the TGDT LDMOS is increased by 112.5 and 54.5%, respectively. Compared with the conventional double trenches LDMOS with rectangle gate, the FOM is similar, but the Q GD is reduced by 45.7%. Simultaneously, the feasible process steps of the TGDT LDMOS are given in this work.

High electric field stress model of n-channel VDMOSFET based on artificial neural network

In VDMOSFETs (Vertical Double-Diffused Metal-Oxide Semiconductor Field-Effect Transistor), in the cases when the voltage at the gate contact comes close to the breakdown voltage, a high electric field (HEF) is formed in the gate oxide. This leads to the generation of fixed and mobile charged defects in the gate oxide and at the silicon/oxide interface. The mechanisms of defects formation are very complex, so it is impossible to create a unique physical model that could describe the behavior of components, i.e., its electrical characteristics, depending on the stress voltage and the stress time. In cases like this, the application of artificial neural network (ANN) has proved to be one of the acceptable solution. In fact, this approach can give the very accurate models for the define range of changes of the input parameters, without going into very complex physical and chemical processes that occur in the structure of the components. All that is necessary to generate the ANN model is the sufficiently large number of the measured data and correct selection of the neural network structure and appropriate training algorithm. In this paper, we have applied the multilayer feedforward neural networks to the model of high electric field stress effects (HEFS) in the n-channel VDMOS power transistor. Experimentally measured transfer characteristics for different times of stress were used to train the neural networks of different configurations. In addition, the influence of several different training algorithms on the accuracy of the model was studied. It is shown that a properly selected neural network structure and training algorithm provide the ANN model of HEFS of the n-channel VDMOS power transistor that very precisely gives its electrical characteristics (transfer characteristic and threshold voltage) for a given stress voltage and temperature in the whole range of the time stress changes from 0 to 150 min.

A Novel Variation of Lateral Doping Technique in SOI LDMOS With Circular Layout

The breakdown characteristics of a practical silicon-on-insulator (SOI) lateral power device are generally limited by the 3-D curvature effect induced by its circular layout. The Conventional 2-D design methods such as 2-D variation of lateral doping (VLD) technique cannot derive optimal device parameters. In this paper, for the first time, a 3-D VLD technique is proposed to suppress the 3-D curvature effect in the lateral power device with circular layout. The 3-D Poisson equation is solved to formulate the optimized doping profile. TCAD tools are employed to verify the model and explore the physic insight. By adding an inversely proportional doping profile onto the conventional linear doping profile, the analytical and numerical results show that the uniform electric field in the drift region and maximized breakdown voltage (BV) are obtained for the SOI lateral double-diffused metal–oxide–semiconductor with circular layout. Furthermore, compared to the 2-D VLD device, the proposed 3-D VLD technique also contributes to excellent on-state characteristics, including the high on-state BV, reduced specific on-resistance, large saturation current, suppressed quasi-saturation effect, improved transconductance, and thus a large Baliga’s figure of merits (BFOM).

Improvement of Deep-Trench LDMOS With Variation Vertical Doping for Charge-Balance Super-Junction

A design concept of variation vertical doping is proposed to upgrade the deep-trench lateral double-diffused metal–oxide–semiconductor field-effect transistor. Due to the proposal, a drift region in the form of charge-balance super-junction is first gained in such a device. Hence, the relationship between the breakdown voltage and the specific on-resistance is significantly improved. Numerical simulations demonstrate that the proposal is valid to increase the theoretical limit of the figure of merit to be about 44.9 MW/cm $^{\textsf {2}}$ , more than twice of that of the prior art. Besides, a feasible realization method is presented and studied.