Double-diffused Metal Oxide Semiconductor Field Research Articles

Novel Si/SiC heterojunction lateral double-diffused metal oxide semiconductor field effect transistor with low specific on-resistance by super junction layer

A novel Si/SiC heterojunction lateral double-diffused metal oxide semiconductor (LDMOS) field effect transistor with the low specific on-resistance (Ron,sp) by super-junction (SJ) layer (Si/SiC SJ-LDMOS) is proposed in this paper. On the basis of using N-Buffer layer to solve substrate assisted depletion effect (SAD), breakdown point transfer terminal technology (BPT) is realized by the deep drain structure of Si/SiC heterojunction and electric field modulation is carried out, which further improves the breakdown voltage (BV) of Si/SiC SJ-LDMOS, alleviates the contradictory relationship between the BV and the Ron,sp. Through ISE TCAD simulation, the result shows that with the same drift region length of 20 μm, the BV is increased from 114 V of conventional SJ-LDMOS (Cov. SJ-LDMOS) and 270 V of SJ-LDMOS with N-Buffer layer (Buffer SJ-LDMOS) to 374 V of Si/SiC SJ-LDMOS, increased by 228% and 38%, respectively. In addition, the Ron,sp of Cov. SJ-LDMOS, Buffer SJ-LDMOS and Si/SiC SJ-LDMOS are 46.26 mΩ cm2, 26.96 mΩ cm2 and 25.85 mΩ cm2, respectively. Moreover, the figure-of-merit (FOM) of proposed Si/SiC SJ-LDMOS device is 5.411 MW/cm2, which means the Si/SiC SJ-LDMOS has a better performance to break the silicon limit. The influence of design parameters on device performance is also discussed.

Novel Vertical Power MOSFET With Step Hk Insulator Close to Super Junction Limit Relationship Between Breakdown Voltage and Specific ON-Resistance by Improving Electric Field Modulation

A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> (Hk) MOSFET concept in this article with the step high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation effect of step Hk insulator, which decreases the specific on-resistance of step Hk VDMOS compared to the conventional Hk VDMOS. The various thickness of the Hk insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of the step Hk VDMOS. Meanwhile, an analytical model for novel step Hk VDMOS is obtained by solving the 2-D Poisson equation in an N-type drift region, and the 2-D Laplace equation in the step Hk region, which can reasonably explain the modulation effect of the step Hk region on the electric field distribution. The results show that the BV of the step Hk VDMOS is increased from 639 V of the conventional Hk VDMOS to 736 V with the same drift length of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42~\mu \text{m}$ </tex-math></inline-formula> . The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.

Breakdown point transfer theory for Si/SiC heterojunction LDMOS with deep drain region

Abstract Heterojunction terminal technology, especially Si/SiC heterojunction, has been widely used in the power semiconductor device. Si/SiC heterojunction LDMOS combines the advantages of Si and SiC while the breakdown point is transferred due to employing the deep drain region structure to improve the BV of the device. Based on the existing research, a new theory about breakdown point transfer terminal technology is proposed for silicon on silicon carbide lateral double-diffused metal oxide semiconductor field effect transistor with deep drain region based on the electric field modulation in this paper for the first time. A concise and efficient analytical theory is presented to predict the breakdown voltage and electric field (E-field) distributions of Si/SiC LDMOS. The mechanism of surface electric field modulated and optimized by breakdown point transfer terminal technology is explained. Introducing the drain region impact factor into the analytical model to decouple the lateral and vertical depletion below the drift region. The analytical model proves that the deep drain region structure can modulate both the lateral and vertical electric field. Meanwhile, the location of the breakdown point can be determined by the E-field distribution at y = TDr and the E-field distribution at y = TSi, which is demonstrated by both theoretical interpreting and simulation. The derivations were verified using the ISE TCAD with a good agreement in the analytical model by changing the key structural parameters of the device. This analytical theory can be applied to other heterojunction power devices.

Novel Power MOSFET With Partial SiC/Si Heterojunction to Improve Breakdown Voltage by Breakdown Point Transfer (BPT) Terminal Technology

In this paper, a new vertical double-diffused metal-oxide semiconductor field effect transistors (VDMOS) is proposed with the partial SiC/Si heterojunction (Partial SiC/Si VDMOS) under the drain electrode in this paper for the first time. The breakdown point transfer technique (BPT) is used to transfer the breakdown point from the radius of curvature is large to the radius of curvature is small in the interface between Pwell and Ndrift region, which causes the longitudinal peak value of electric field to be raised, and the higher breakdown voltage (BV) can be obtained. At the same time, the formation of highly doped N-type silicon trench alleviates interface state problems caused by current flowing through SiC/Si heterojunction and further optimized the whole SiC/Si heterojunction (SiC/Si VDMOS). The limit line of the silicon has been broken because the result is improved between the BV and the specific on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ). Compared with the conventional Si VDMOS, the BV is increased from 238V to 342V, and the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> is reduced from 14.24mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to 13.92mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

A novel silicon (Si) on silicon carbide (SiC) lateral double-diffused metal oxide semiconductor field effect transistor with deep drain region is proposed. Its main idea is transferring the breakdown point and utilising the high critical electric field of SiC material to suppress the curvature effect of the drain, which eventually alleviates the trade-off relationship between breakdown voltage (BV) and specific on-resistance ( R on,sp ). Through the TCAD simulation, the results show that the BV is significantly improved from 240 V for conventional Si lateral double-diffused metal oxide semiconductor (LDMOS) to 384 V for the proposed structure with the drift region length of 20 μm, increased by 60%. The figure-of-merit of the conventional Si LDMOS and the Si/SiC LDMOS are 2.04 and 4.26 MW/cm 2 , respectively. It indicates that the proposed structure has better performance than the Si counterpart. The influences of design parameters and interfacial charges on the device performance are also discussed in this work.

Split‐gate LDMOS with double vertical field plates

In this study, a novel split-gate lateral double-diffused metal oxide semiconductor field effect transistor with double vertical field plates (SG DVFP LDMOS) is proposed. The first feature of the SG DVFP LDMOS is that the SG with gradient gate oxide is introduced. The SG not only optimises the bulk electric field distributions to increase the breakdown voltage (BV) but also reduces the gate-drain charge (Q GD) owing to the thick gate oxide. The second feature of the SG DVFP LDMOS is the presence of the DVFP and P-pillar. They modulate the bulk electric field distributions and assist to deplete the drift region. So the specific on-resistance (R on,sp) is decreased and the BV is improved. The source vertical field plate reduces the contact region between the gate and drain, thereby the Q GD is reduced. Compared with the conventional SG LDMOS and rectangle-gate DVFP LDMOS, the figure of merit FOM1 of SG DVFP LDMOS is increased by 123.2 and 86.6%, and the loss figure of merit FOM2 is enhanced to 16.9 and 37.2%. Simultaneously, the key process steps of the SG DVFP LDMOS are proposed.

Theory Analyses of SJ-LDMOS With Multiple Floating Buried Layers Based on Bulk Electric Field Modulation

A new theory about terminal technology is proposed for superjunction lateral double-diffused metal–oxide–semiconductor field effect transistors with multiple floating buried layers (MFBL SJ-LDMOS) based on the bulk electric field (E-field) modulation in this paper for the first time. A concise and efficient analytical theory is presented to predict the vertical voltage and bulk E-field distributions of MFBL SJ-LDMOS. The analytical formulas for the breakdown voltage (BV) and the vertical peak E-field of MFBL SJ-LDMOS are derived in the closed-form equations, which starts from a single floating buried layer for the vertical E-field modulation, extending this theory to predict the vertical E-field peaks and vertical voltage distributions between the MFBLs. Quantitative analytical description has been given to explain the bulk E-field modulation for the MFBL. Moreover, the optimal spacing and the maximum BV are procedurally predicted. All analytical results are well verified by the 3-D numerical simulations, proving the applicability of the method presented in other power devices with MFBL including MFBL LDMOS, MFBL lateral insulated gate bipolar transistor, and MFBL diode.

Design of a novel triple reduced surface field LDMOS with partial linear variable doping n-type top layer

A novel triple reduced surface field (RESURF) lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) with partial linear variable doping (LVD) N-type top (N-top) layer is proposed in this paper. Compared with the conventional triple RESURF LDMOS, a partial LVD N-top layer is introduced in the surface of N-well, providing a low on-resistance conduction path and leading to an optimized surface electric field, which alleviates the inherent tradeoff between the breakdown voltage (BV) and specific on-resistance (Ron,sp). With the n-drift region length of 70 μm, the novel triple RESURF LDMOS obtains a high BV of 847 V and a low Ron,sp of 79 mΩ cm2 which are 76 V higher and 46 mΩ cm2 lower than those of the conventional triple RESURF LDMOS. Therefore, the novel triple RESURF LDMOS can greatly improve the tradeoff between BV and Ron,sp. Furthermore, compared with the other existing technologies in the high BV level, the novel triple RESURF LDMOS can achieve a highest figure of merit (FOM, defined as BV2/Ron,sp) of 9.08 MW/cm2 and the conventional RESURF silicon limits are broken.

Electric field optimized LDMOST using multiple decrescent and reverse charge regions

A lateral double-diffused metal—oxide—semiconductor field effect transistor (LDMOST) with multiple n-regions in the p-substrate is investigated in detail. Because of the decrescent n-regions, the electric field distribution is higher and more uniform, and the breakdown voltage of the new structure is increased by 95%, in comparison with that of a conventional counterpart without substrate n-regions. Based on the trade-off between the breakdown voltage and the on-resistance, the optimal number of n-regions and the other key parameters are achieved. Furthermore, sensitivity research shows that the breakdown voltage is relatively sensitive to the drift region doping and the n-regions' lengths.

Breakdown Characteristics of High-Side Lateral Double-Diffused Metal Oxide Semiconductor Devices

In this paper, we discuss the breakdown characteristics of an LDMOSFET (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure for the optimization of engineering parameters such as the gap between the DEEP N-WELL and the source region and the doping concentration of the N(ADJUST)-layer. The fabricated device exhibits the breakdown voltage (BVdss) over 110 V and the specific on-resistance as low as 2.20 mOmega cm2. The robust breakdown characteristics seem to be due to the migration of the location wherein maximum impact ionization occurs from the gate region to the drain side, which was confirmed by the numerical simulation which verifies that the maximum impact ionization rate of the proposed structure is 2.44 x 10(16) cm(-3) s(-1), while that of the conventional structure being 6.69 x 10(19) cm(-3) s(-1).

Impact of Drift Gap, &lt;I&gt;N&lt;/I&gt;-Layer, and Deep N&lt;SUP&gt;+&lt;/SUP&gt; Sinker on Breakdown Voltage and Saturation Current of Lateral Double-Diffused Metal Oxide Semiconductor Transistor

In this paper, we discuss on the optimal design of a High-Side n-channel Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET) whose breakdown voltage is over 100 V with 0.35 microm Bipolar-CMOS-DMOS (BCD) process. The proposed nLDMOSFET has been fabricated and tested in order to confirm the features of a deep N+ sinker and a gap of between the drift region (DEEP N-WELL) and the center of the source. The surface is implanted by the N-layer for high breakdown voltage and simultaneously the low specific on-resistance. The computer simulation of the proposed High-Side LDMOS exhibits BVdss of 115 V and Ron,sp of as low as 2.20 m ohms cm2, which is consistent with the experimental results.

High-Side nLDMOS Design for Ensuring Breakdown Voltages Over 100 V

We propose a novel n-channel LDMOSFET (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure with a breakdown voltage over 100 V under the thermal budget for the conventional 0.35 microm BCD process. We varied the gap between the DEEP N-WELL and the center of the source for optimization and optimized the doping concentration under the surface by the N(ADJUST)-layer in an effort to obtain high breakdown voltage and simultaneously the low specific on-resistance. The fabricated samples of the proposed High-Side n-channel LDMOS structure exhibit BVdss of 120 V and the specific on-resistance of 2.40 m ohms cm2. We also observed the shift of maximum impact ionization rate from the gate region to the drain side which is considered to strengthen the breakdown characteristics. The numerical simulation revealed that the maximum impact ionization rate of the proposed structure can be reduced down to 18.61 cm(-3) s(-1), while that of the conventional structure being as high as 25.44 cm(-3) s(-1).

High-side N-channel LDMOS for a High Breakdown Voltage

We propose a novel n-channel LDMOSFET (lateral double-diffused metal oxide semiconductor field effect transistor) structure with a breakdown voltage over 100 V, which was fabricated under the thermal budget of the conventional 0.35-μm industry process. We optimized the engineering parameters, such as the distance of the gap between the DEEP N-WELL and the source region, as well as the doping concentration of the NADJUST-layer, for achieving both the high breakdown voltage and the low specific on-resistance. The fabricated device exhibits a breakdown voltage (BVdss) over 110 V and a specific on-resistance as low as 2.20 mΩ·cm. The robust breakdown characteristics are due to the migration of the location wherein maximum impact ionization occurs from the gate region to the drain side. The numerical simulation revealed that the maximum impact ionization rate of the proposed structure was 2.44 × 10 cm−3s−1 while that of the conventional structure was 6.69 × 10 cm−3s−1.

A Novel Super-Junction Lateral Double-Diffused Metal—Oxide—Semiconductor Field Effect Transistor with n-Type Step Doping Buffer Layer

A novel super-junction lateral double-diffused metal–oxide–semiconductor field effect transistor (SJ-LDMOSFET) with n-type step doping buffer layer is proposed. The step doping buffer layer almost completely eliminates the substrate-assisted depletion effect, modulates lateral electric field and achieves nearly uniform surface field. On the other hand, the buffer layer also provides another conductive path and reduces on-state resistance. In short, the proposed LDMOSFET improves trade-off performance between breakdown voltage (BV) and specific on-state resistance Ron,sp. Compared with the conventional SJ-LDMOSFET, the simulation results indicate that the BV of the SSJ-LDMOSFET is increased from saturation voltage 121.7V to 644.9V; at the same time, the specific on-state resistance is decreased from 0.314Ω·cm2 to 0.14Ω·cm2 by virtue of 3D numerical simulations using ISE when the drift region length and the step number are taken as 48μm and 3, respectively.

A novel high performance stacked LDD RF LDMOSFET

A novel silicon RF lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) structure, using a simple yet effective concept of stacked lightly doped drain (LDD), is proposed. The stacked layers of LDD minimizes the on-state resistance of the transistor due to the n+ doping used in the top LDD layer, and also raises the device breakdown voltage due to the charge compensation in the composite LDD region. Therefore, for the same blocking voltage rating, the stacked LDD structure allows the LDMOSFET to have a higher current handling capability. This in turn causes the transconductance Gm to be higher, leading to higher RF performance for the power device. Measured results show that a 67% improvement in I/sub dsat/ and a 16% improvement in forward blocking voltage are obtained. Furthermore, the new device achieves an increase in transconductance of 145% and improves cut-off frequency by 108% at a gate voltage of 10 V.

Molybdenum Film Technology For Power Metal Oxide Semiconductor Field Effect Transistor Gate Electrode Applications

Molybdenum (Mo) film as a gate electrode for high-frequency power metal oxide semiconductor field effect transistor (MOSFET) has been investigated. The Mo films were deposited by sputtering in Ar ambient. The Mo films properties depend greatly on the substrate temperature. An accurate pattern was realized for Mo film. Stability and reliability of Mo gates for high-frequency power vertical double-diffused metal oxide semiconductor field effect transistors (VDMOSFETs) are as good as those of polysilicon gates. The shift of threshold voltage is below ±35 mV and the change of gate-source leakage current is less than 5 nA under the stress condition of ±5 MV/cm for 100 h at 250°C. Power gain and drain efficiency improvement of Mo gates for VDMOSFETs have been obtained.